Datasheet > MPC92429FN

MPC92429FN

更新时间： 2024-01-01 02:01:12

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		时钟
页数	文件大小	规格书
12页	217K
描述
400 MHz Low Voltage PECL Clock Synthesizer

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MPC92429FN 技术参数

生命周期：	Transferred	零件包装代码：	QLCC
包装说明：	QCCJ, LDCC28,.5SQ	针数：	28
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.22
JESD-30 代码：	S-PQCC-J28	长度：	11.505 mm
端子数量：	28	最高工作温度：	70 °C
最低工作温度：		最大输出时钟频率：	400 MHz
封装主体材料：	PLASTIC/EPOXY	封装代码：	QCCJ
封装等效代码：	LDCC28,.5SQ	封装形状：	SQUARE
封装形式：	CHIP CARRIER	电源：	3.3 V
主时钟/晶体标称频率：	20 MHz	认证状态：	Not Qualified
座面最大高度：	4.57 mm	子类别：	Clock Generators
最大压摆率：	100 mA	最大供电电压：	3.465 V
最小供电电压：	3.135 V	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	QUAD
宽度：	11.505 mm	uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, OTHER
Base Number Matches：	1

MPC92429FN 数据手册

Order Number: MPC92429/D

Rev 0, 09/2003

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

400 MHz Low Voltage PECL

Clock Synthesizer

MPC92429

The MPC92429 is a 3.3V compatible, PLL based clock synthesizer

targeted for high performance clock generation in mid-range to

high-performance telecom, networking and computing applications. With

output frequencies from 25 MHz to 400 MHz and the support of differential

PECL output signals the device meets the needs of the most demanding

clock applications.

400 MHZ LOW VOLTAGE

CLOCK SYNTHESIZER

Features

• 25 MHz to 400 MHz synthesized clock output signal

• Differential PECL output

• LVCMOS compatible control inputs

• On-chip crystal oscillator for reference frequency generation

• 3.3V power supply

• Fully integrated PLL

• Minimal frequency overshoot

• Serial 3-wire programming interface

• Parallel programming interface for power-up

• 32 lead LQFP and 28 PLCC packaging

• SiGe Technology

FN SUFFIX

28--LEAD PLCC PACKAGE

CASE 776

• Ambient temperature range 0°C to +70°C

• Pin and function compatible to the MC12429 and MPC9229

Functional Description

FA SUFFIX

32 LEAD LQFP PACKAGE

CASE 873A

The internal crystal oscillator uses the external quartz crystal as the

basis of its frequency reference. The frequency of the internal crystal

oscillator is divided by 16 and then multiplied by the PLL. The VCO within

the PLL operates over a range of 200 to 400 MHz. Its output is scaled by a

divider that is configured by either the serial or parallel interfaces. The

crystal oscillator frequency f

post-divider N determine the output frequency.

, the PLL feedback-divider M and the PLL

XTAL

The feedback path of the PLL is internal. The PLL adjusts the VCO output frequency to be⋅M times the reference frequency by

adjusting the VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve phase lock.

The PLL will be stable if the VCO frequency is within the specified VCO frequency range (200 to 400 MHz). The M-value must be

programmed by the serial or parallel interface.

The PLL post-divider N is configured through either the serial or the parallel interfaces, and can provide one of four division

ratios (1, 2, 4, or 8). This divider extends performance of the part while providing a 50% duty cycle. The output driver is driven

differentially from the output divider, and is capable of driving a pair of transmission lines terminated 50Ω to V

– 2.0V. The

positive supply voltage for the internal PLL is separated from the power supply for the core logic and output drivers to minimize

noise induced jitter.

The configuration logic has two sections: serial and parallel. The parallel interface uses the values at the M[8:0] and N[1:0]

inputs to configure the internal counters. It is recommended on system reset to hold the P_LOAD input LOW until power becomes

valid. On the LOW–to–HIGH transition of P_LOAD, the parallel inputs are captured. The parallel interface has priority over the

serial interface. Internal pullup resistors are provided on the M[8:0] and N[1:0] inputs prevent the LVCMOS compatible control

inputs from floating.

The serial interface centers on a fourteen bit shift register. The shift register shifts once per rising edge of the S_CLOCK input.

The serial input S_DATA must meet setup and hold timing as specified in the AC Characteristics section of this document. The

configuration latches will capture the value of the shift register on the HIGH–to–LOW edge of the S_LOAD input. See the

programming section for more information. The TEST output reflects various internal node values, and is controlled by the T[2:0]

bits in the serial data stream. In order to minimize the PLL jitter, it is recommended to avoid active signal on the TEST output.

 Motorola, Inc. 2003

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与MPC92429FN相关器件

型号	品牌	获取价格	描述	数据表
MPC92432	MOTOROLA	获取价格	1360 MHz Dual Output LVPECL Clock Synthesizer
MPC92432	IDT	获取价格	1360 MHz Dual Output LVPECL Clock Synthesizer Fully integrated PLL
MPC92432AER2	NXP	获取价格	1360MHz, OTHER CLOCK GENERATOR, PQFP48, LEAD FREE, LQFP-48
MPC92432AER2	IDT	获取价格	Clock Generator, 1360MHz, PQFP48, LEAD FREE, LQFP-48
MPC92432FA	MOTOROLA	获取价格	1360 MHz Dual Output LVPECL Clock Synthesizer
MPC92432FA	NXP	获取价格	1360MHz, OTHER CLOCK GENERATOR, PQFP48, LQFP-48
MPC92432FAR2	NXP	获取价格	1360MHz, OTHER CLOCK GENERATOR, PQFP48, LQFP-48
MPC92433	FREESCALE	获取价格	1428 MHz Dual Output LVPECL Clock Synthesizer
MPC92433AER2	NXP	获取价格	1428MHz, OTHER CLOCK GENERATOR, PQFP48, ROHS COMPLIANT, LQFP-48
MPC92433AER2	IDT	获取价格	TQFP-48, Reel

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