Datasheet > MPC92432AER2

MPC92432AER2

更新时间： 2024-11-26 17:29:15

品牌	Logo	应用领域
恩智浦 - NXP		时钟外围集成电路晶体
页数	文件大小	规格书
20页	412K
描述
1360MHz, OTHER CLOCK GENERATOR, PQFP48, LEAD FREE, LQFP-48

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MPC92432AER2 技术参数

是否Rohs认证：	符合	生命周期：	Transferred
零件包装代码：	QFP	包装说明：	LEAD FREE, LQFP-48
针数：	48	Reach Compliance Code：	unknown
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.5	JESD-30 代码：	S-PQFP-G48
长度：	7 mm	湿度敏感等级：	3
端子数量：	48	最高工作温度：	85 °C
最低工作温度：	-40 °C	最大输出时钟频率：	1360 MHz
封装主体材料：	PLASTIC/EPOXY	封装代码：	LFQFP
封装形状：	SQUARE	封装形式：	FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）：	260	主时钟/晶体标称频率：	20 MHz
认证状态：	Not Qualified	座面最大高度：	1.6 mm
最大供电电压：	3.465 V	最小供电电压：	3.135 V
标称供电电压：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	40
宽度：	7 mm	uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, OTHER
Base Number Matches：	1

MPC92432AER2 数据手册

MPC92432

Rev 2, 06/2005

Freescale Semiconductor

Technical Data

1360 MHz Dual Output LVPECL Clock

Synthesizer

MPC92432

The MPC92432 is a 3.3 V compatible, PLL based clock synthesizer targeted

for high performance clock generation in mid-range to high-performance

telecom, networking, and computing applications. With output frequencies from

21.25 MHz to 1360 MHz and the support of two differential PECL output signals,

the device meets the needs of the most demanding clock applications.

1360 MHz LOW VOLTAGE

CLOCK SYNTHESIZER

Features

•

21.25 MHz to 1360 MHz synthesized clock output signal

Two differential, LVPECL-compatible high-frequency outputs

Output frequency programmable through 2-wire I²C bus or parallel interface

On-chip crystal oscillator for reference frequency generation

Alternative LVCMOS compatible reference clock input

Synchronous clock stop functionality for both outputs

LOCK indicator output (LVCMOS)

(1)

FA SUFFIX

48-LEAD LQFP PACKAGE

CASE 932-03

LVCMOS compatible control inputs

Fully integrated PLL

3.3-V power supply

48-lead LQFP

(2)

AE SUFFIX

48-lead Pb-free package available

48-LEAD LQFP PACKAGE

Pb-FREE PACKAGE

CASE 932-03

SiGe Technology

Ambient temperature range: –40°C to +85°C

Applications

•

Programmable clock source for server, computing, and telecommunication systems

Frequency margining

Oscillator replacement

Functional Description

The MPC92432 is a programmable high-frequency clock source (clock synthesizer). The internal PLL generates a high-

frequency output signal based on a low-frequency reference signal. The frequency of the output signal is programmable and can

be changed on the fly for frequency margining purpose.

The internal crystal oscillator uses the external quartz crystal as the basis of its frequency reference. Alternatively, a LVCMOS

compatible clock signal can be used as a PLL reference signal. The frequency of the internal crystal oscillator is divided by a

selectable divider and then multiplied by the PLL. The VCO within the PLL operates over a range of 1360 to 2720 MHz. Its output

is scaled by a divider that is configured by either the I²C or parallel interfaces. The crystal oscillator frequency f_XTAL, the PLL pre-

divider P, the feedback-divider M, and the PLL post-divider N determine the output frequency. The feedback path of the PLL is

internal.

The PLL post-divider N is configured through either the I²C or the parallel interfaces, and can provide one of six division ratios

(2, 4, 8, 16, 32, 64). This divider extends the performance of the part while providing a 50% duty cycle. The high-frequency out-

puts, Q_Aand Q_B, are differential and are capable of driving a pair of transmission lines terminated 50 Ω to V_CC– 2.0 V. The second

high-frequency output, Q_B, can be configured to run at either 1x or 1/2x of the clock frequency or the first output (Q_A). The positive

supply voltage for the internal PLL is separated from the power supply for the core logic and output drivers to minimize noise

induced jitter.

The configuration logic has two sections: I²C and parallel. The parallel interface uses the values at the M[9:0], NA[2:0], NB,

and P parallel inputs to configure the internal PLL dividers. The parallel programming interface has priority over the serial I²C

interface. The serial interface is I²C compatible and provides read and write access to the internal PLL configuration registers.

The lock state of the PLL is indicated by the LVCMOS-compatible LOCK output.

1. FA suffix: leaded terminations.

2. AE suffix: lead-free, EPP and RoHS-compliant.

12 3 4 5 6 7...20

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与MPC92432AER2相关器件

型号	品牌	获取价格	描述	数据表
MPC92432FA	MOTOROLA	获取价格	1360 MHz Dual Output LVPECL Clock Synthesizer
MPC92432FA	NXP	获取价格	1360MHz, OTHER CLOCK GENERATOR, PQFP48, LQFP-48
MPC92432FAR2	NXP	获取价格	1360MHz, OTHER CLOCK GENERATOR, PQFP48, LQFP-48
MPC92433	FREESCALE	获取价格	1428 MHz Dual Output LVPECL Clock Synthesizer
MPC92433AER2	NXP	获取价格	1428MHz, OTHER CLOCK GENERATOR, PQFP48, ROHS COMPLIANT, LQFP-48
MPC92433AER2	IDT	获取价格	TQFP-48, Reel
MPC92433FA	IDT	获取价格	Clock Generator, 1428MHz, PQFP48, LQFP-48
MPC92433FAR2	NXP	获取价格	1428MHz, OTHER CLOCK GENERATOR, PQFP48, LQFP-48
MPC92439	IDT	获取价格	900MHz, Low Voltage, LVPECL Clock Syntheesizer
MPC92439AC	IDT	获取价格	900MHz, Low Voltage, LVPECL Clock Syntheesizer

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