Datasheet > MPC92469AC

MPC92469AC

更新时间： 2024-11-04 21:18:31

品牌	Logo	应用领域
艾迪悌 - IDT		时钟外围集成电路晶体
页数	文件大小	规格书
13页	576K
描述
TQFP-32, Tray

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技术参数
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MPC92469AC 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	TQFP
包装说明：	LEAD FREE, LQFP-32	针数：	32
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	8.62
JESD-30 代码：	S-PQFP-G32	JESD-609代码：	e3
长度：	7 mm	湿度敏感等级：	3
端子数量：	32	最高工作温度：	70 °C
最低工作温度：		最大输出时钟频率：	400 MHz
封装主体材料：	PLASTIC/EPOXY	封装代码：	LQFP
封装等效代码：	QFP32,.35SQ,32	封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE	峰值回流温度（摄氏度）：	260
电源：	3.3 V	主时钟/晶体标称频率：	20 MHz
认证状态：	Not Qualified	座面最大高度：	1.6 mm
子类别：	Clock Generators	最大压摆率：	95 mA
最大供电电压：	3.465 V	最小供电电压：	3.135 V
标称供电电压：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	MATTE TIN	端子形式：	GULL WING
端子节距：	0.8 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	30	宽度：	7 mm
uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, OTHER	Base Number Matches：	1

MPC92469AC 数据手册

400MHz Low Voltage PECL Clock

Synthesizer w/Spread Spectrum

MPC92469

Product Discontinuance Notice – Last Time Buy Expires on (1/31/2014)

DATASHEET

The MPC92469 is a 3.3 V compatible, PLL based clock synthesizer targeted

for high performance clock generation in mid-range to high-performance tele-

com, networking and computing applications. With output frequencies from

25 MHz to 400 MHz and the support of differential PECL output signals the

device meets the needs of the most demanding clock applications.

Features

•

25 MHz to 400 MHz synthesized clock output signal

Differential PECL output

400 MHz LOW VOLTAGE

CLOCK SYNTHESIZER

w/SPREAD SPECTRUM

LVCMOS compatible control inputs

On-chip crystal oscillator for reference frequency generation

Spread Spectrum output for EMI reduction

3.3 V power supply

Fully integrated PLL

Minimal frequency overshoot

Serial 3-wire programming interface

Parallel programming interface for power-up

32-lead LQFP packaging

FA SUFFIX

32-LEAD LQFP PACKAGE

CASE 873A-03

32-lead Pb-free package available

SiGe Technology

Ambient temperature range 0C to +70C

Pin compatible to the MC12429, MPC9229, MPC92429, and ICS84329

AC SUFFIX

32-LEAD LQFP PACKAGE

Pb-FREE PACKAGE

CASE 873A-03

Functional Description

The internal crystal oscillator uses the external quartz crystal as the basis of

its frequency reference. The frequency of the internal crystal oscillator is divided

by 16 and then multiplied by the PLL. The VCO within the PLL operates over a

range of 400 to 800 MHz. Its output is scaled by a divider that is configured by

either the serial or parallel interfaces. The crystal oscillator frequency f_XTAL, the

PLL feedback-divider M and the PLL post-divider N determine the output frequency.

The feedback path of the PLL is internal. The PLL adjusts the VCO output frequency to be 2M times the reference frequency

by adjusting the VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve phase

lock. The PLL will be stable if the VCO frequency is within the specified VCO frequency range (400 to 800 MHz). The M-value

must be programmed by the serial or parallel interface.

The PLL post-divider N is configured through either the serial or the parallel interfaces, and can provide one of four division

ratios (1, 2, 4, or 8). This divider extends performance of the part while providing a 50% duty cycle. The output driver is driven

differentially from the output divider, and is capable of driving a pair of transmission lines terminated 50  to V_CC– 2.0 V. The

positive supply voltage for the internal PLL is separated from the power supply for the core logic and output drivers to minimize

noise induced jitter.

The configuration logic has two sections: serial and parallel. The parallel interface uses the values at the M[8:0] and N[1:0]

inputs to configure the internal counters. It is recommended on system reset to hold the P_LOAD input LOW until power becomes

valid. On the LOW-to-HIGH transition of P_LOAD, the parallel inputs are captured. The parallel interface has priority over the

serial interface. Internal pullup resistors are provided on the M[8:0] and N[1:0] inputs prevent the LVCMOS compatible control

inputs from floating.

The serial interface centers on a eighteen bit shift register. The shift register shifts once per rising edge of the S_CLOCK input.

The serial input S_DATA must meet setup and hold timing as specified in the AC Characteristics section of this document. The

configuration latches will capture the value of the shift register on the HIGH-to-LOW edge of the S_LOAD input. See PROGRAM-

MING INTERFACE for more information. The TEST output reflects various internal node values, and is controlled by the T[2:0]

bits in the serial data stream. In order to minimize the PLL jitter, it is recommended to avoid active signal on the TEST output.

MPC92469 REVISION 4 FEBRUARY 6, 2013

12 3 4 5 6 7...13

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与MPC92469AC相关器件

型号	品牌	获取价格	描述	数据表
MPC92469ACR2	IDT	获取价格	Clock Generator, PQFP32
MPC92474AC	NXP	获取价格	700 MHz, OTHER CLOCK GENERATOR, PQFP48, LEAD FREE, LQFP-48
MPC92474AC	IDT	获取价格	Clock Generator, 700MHz, PQFP48, LEAD FREE, LQFP-48
MPC92474FA	IDT	获取价格	Clock Generator, 700MHz, PQFP48, LQFP-48
MPC9259	MOTOROLA	获取价格	900 MHz LOW VOLTAGE LVDS CLOCK SYNTHESIZER
MPC9259	FREESCALE	获取价格	900 MHz LOW VOLTAGE LVDS CLOCK SYNTHESIZER
MPC9259D	FREESCALE	获取价格	900 MHz LOW VOLTAGE LVDS CLOCK SYNTHESIZER
MPC9259D	MOTOROLA	获取价格	900 MHz LOW VOLTAGE LVDS CLOCK SYNTHESIZER
MPC9259FA	FREESCALE	获取价格	900 MHz LOW VOLTAGE LVDS CLOCK SYNTHESIZER
MPC9259FA	MOTOROLA	获取价格	900 MHz LOW VOLTAGE LVDS CLOCK SYNTHESIZER

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