Datasheet > MPC9230FNR2

MPC9230FNR2

更新时间： 2024-11-04 21:04:15

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		/
页数	文件大小	规格书
12页	168K
描述
Clock Generator, 800MHz, CMOS, PQCC28, PLASTIC, LCC-28

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MPC9230FNR2 技术参数

是否Rohs认证：	不符合	生命周期：	Transferred
包装说明：	QCCJ, LDCC28,.5SQ	Reach Compliance Code：	unknown
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.81	JESD-30 代码：	S-PQCC-J28
长度：	11.505 mm	端子数量：	28
最高工作温度：	70 °C	最低工作温度：
最大输出时钟频率：	800 MHz	封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCJ	封装等效代码：	LDCC28,.5SQ
封装形状：	SQUARE	封装形式：	CHIP CARRIER
电源：	3.3 V	主时钟/晶体标称频率：	20 MHz
认证状态：	Not Qualified	座面最大高度：	4.57 mm
子类别：	Clock Generators	最大压摆率：	110 mA
最大供电电压：	3.465 V	最小供电电压：	3.135 V
标称供电电压：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子形式：	J BEND	端子节距：	1.27 mm
端子位置：	QUAD	宽度：	11.505 mm
uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, OTHER	Base Number Matches：	1

MPC9230FNR2 数据手册

Order Number: MPC9230/D

Rev 3, 03/2003

SEMICONDUCTOR TECHNICAL DATA

The MPC9230 is a 3.3V compatible, PLL based clock synthesizer

targeted for high performance clock generation in mid-range to

high-performance telecom, networking and computing applications. With

output frequencies from 50 MHz to 800 MHz and the support of differential

PECL output signals the device meets the needs of the most demanding

clock applications.

800 MHZ LOW VOLTAGE

CLOCK SYNTHESIZER

Features

• 50 MHz to 800 MHz synthesized clock output signal

• Differential PECL output

• LVCMOS compatible control inputs

• On-chip crystal oscillator for reference frequency generation

• Alternative LVCMOS compatible reference clock input

• 3.3V power supply

FN SUFFIX

28 LEAD PLCC PACKAGE

CASE 776

• Fully integrated PLL

• Minimal frequency overshoot

• Serial 3-wire programming interface

• Parallel programming interface for power-up

• 32 lead LQFP and 28 PLCC packaging

• SiGe Technology

FA SUFFIX

32 LEAD LQFP PACKAGE

CASE 873A

• Ambient temperature range 0°C to +70°C

• Pin and function compatible to the MC12430

Functional Description

The internal crystal oscillator uses the external quartz crystal as the basis of its frequency reference. The frequency of the

internal crystal oscillator is divided by 16 and then multiplied by the PLL. The VCO within the PLL operates over a range of 800 to

1600 MHz. Its output is scaled by a divider that is configured by either the serial or parallel interfaces. The crystal oscillator

frequency f , the PLL feedback-divider M and the PLL post-divider N determine the output frequency.

XTAL

The feedback path of the PLL is internal. The PLL adjusts the VCO output frequency to be 8 M times the reference frequency

by adjusting the VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve phase

lock. The PLL will be stable if the VCO frequency is within the specified VCO frequency range (800 to 1600 MHz). The M-value

must be programmed by the serial or parallel interface.

The PLL post-divider N is configured through either the serial or the parallel interfaces, and can provide one of four division

ratios (1, 2, 4, or 8). This divider extends performance of the part while providing a 50% duty cycle. The output driver is driven

differentially from the output divider, and is capable of driving a pair of transmission lines terminated 50Ω to V

positive supply voltage for the internal PLL is separated from the power supply for the core logic and output drivers to minimize

noise induced jitter.

– 2.0V. The

The configuration logic has two sections: serial and parallel. The parallel interface uses the values at the M[8:0] and N[1:0]

inputs to configure the internal counters. It is recommended on system reset to hold the P_LOAD input LOW until power becomes

valid. On the LOW–to–HIGH transition of P_LOAD, the parallel inputs are captured. The parallel interface has priority over the

serial interface. Internal pullup resistors are provided on the M[8:0] and N[1:0] inputs prevent the LVCMOS compatible control

inputs from floating.

The serial interface centers on a fourteen bit shift register. The shift register shifts once per rising edge of the S_CLOCK input.

The serial input S_DATA must meet setup and hold timing as specified in the AC Characteristics section of this document. The

configuration latches will capture the value of the shift register on the HIGH–to–LOW edge of the S_LOAD input. See the

programming section for more information. The TEST output reflects various internal node values, and is controlled by the T[2:0]

bits in the serial data stream. In order to minimize the PLL jitter, it is recommended to avoid active signal on the TEST output.

Motorola, Inc. 2003

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与MPC9230FNR2相关器件

型号	品牌	获取价格	描述	数据表
MPC9239	FREESCALE	获取价格	900 MHz Low Voltage LVPECL Clock Synthesizer
MPC9239AC	FREESCALE	获取价格	900 MHz Low Voltage LVPECL Clock Synthesizer
MPC9239EI	FREESCALE	获取价格	900 MHz Low Voltage LVPECL Clock Synthesizer
MPC9239EI	NXP	获取价格	900 MHz, OTHER CLOCK GENERATOR, PQCC28, LEAD FREE, PLASTIC, LCC-28
MPC9239EIR2	NXP	获取价格	900MHz, OTHER CLOCK GENERATOR, PQCC28, LEAD FREE, PLASTIC, LCC-28
MPC9239FA	MOTOROLA	获取价格	Clock Generator, 900MHz, CMOS, PQFP32, LQFP-32
MPC9239FA	FREESCALE	获取价格	900 MHz Low Voltage LVPECL Clock Synthesizer
MPC9239FA	NXP	获取价格	900MHz, OTHER CLOCK GENERATOR, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, MS-026BBA,
MPC9239FN	NXP	获取价格	IC,MISCELLANEOUS CLOCK GENERATOR,LDCC,28PIN,PLASTIC
MPC9239FN	MOTOROLA	获取价格	Clock Generator, 900MHz, CMOS, PQCC28, PLASTIC, LCC-28

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