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MPC2002SG50 PDF预览

MPC2002SG50

更新时间: 2024-10-28 22:12:39
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 存储内存集成电路静态存储器信息通信管理PC
页数 文件大小 规格书
14页 238K
描述
256KB and 512KB BurstRAM Secondary Cache Module for PowerPC - Based Systems

MPC2002SG50 技术参数

生命周期:Obsolete零件包装代码:DIMM
包装说明:DIMM, DIMM136针数:136
Reach Compliance Code:unknownECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.84
最长访问时间:14 ns其他特性:BYTE WRITE; BURST COUNTER; SELF-TIMED WRITE
备用内存宽度:72JESD-30 代码:R-XDMA-N136
内存密度:2359296 bit内存集成电路类型:CACHE SRAM MODULE
内存宽度:36功能数量:1
端口数量:1端子数量:136
字数:65536 words字数代码:64000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:64KX36
输出特性:3-STATE可输出:YES
封装主体材料:UNSPECIFIED封装形状:RECTANGULAR
封装形式:MICROELECTRONIC ASSEMBLY并行/串行:PARALLEL
认证状态:Not Qualified最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:BICMOS
温度等级:COMMERCIAL端子形式:NO LEAD
端子位置:DUALBase Number Matches:1

MPC2002SG50 数据手册

 浏览型号MPC2002SG50的Datasheet PDF文件第2页浏览型号MPC2002SG50的Datasheet PDF文件第3页浏览型号MPC2002SG50的Datasheet PDF文件第4页浏览型号MPC2002SG50的Datasheet PDF文件第5页浏览型号MPC2002SG50的Datasheet PDF文件第6页浏览型号MPC2002SG50的Datasheet PDF文件第7页 
Order this document  
by MPC2002/D  
SEMICONDUCTOR TECHNICAL DATA  
MPC2002  
256KB and 512KB BurstRAM  
Secondary Cache Module for  
PowerPC – Based Systems  
MPC2003  
(Formerly MCM72MS32/64)  
136–LEAD DIMM  
CASE 1104–01  
TOP VIEW  
The MPC2002SG and MPC2003SG are designed to provide a burstable, high  
performance, 256K/512K L2 cache for the PowerPC 60x processors. The mod-  
ules are configured as 32K x 72 and 64K x 72 bits in a 136 pin dual readout single  
inline memory module (DIMM). The module uses four of Motorola’s  
MCM67M518 or MCM67M618 BiCMOS BurstRAMs.  
1
Bursts can be initiated with either transfer start processor (TSP) or transfer  
start controller (TSC). Subsequent burst addresses are generated internal to the  
BurstRAM by the burst address advance (BAA) pin.  
Write cycles are internally self timed and are initiated by the rising edge of the  
clock (K) input. Eight write enables are provided for byte write control.  
The cache family is designed to interface with the PowerPC 60x bus and re-  
quires external tag.  
PD0 – PD2 are reserved for density and speed identification.  
PowerPC–style Burst Counter on Board  
Dual Readout SIMM for Circuit Density  
Single 5 V ± 5% Power Supply  
34  
35  
All Inputs and Outputs are TTL Compatible  
Three State Outputs  
Byte Parity  
Byte Write Capability  
Fast Module Clock Rates: 66 MHz, 60 MHz, 50MHz  
Decoupling Capacitors for each Fast Static RAM  
High Quality Multi–Layer FR4 PWB With Separate Power and Ground Planes  
I/Os are 3.3 V Compatible  
68  
BurstRAM is a trademark of Motorola.  
PowerPC and PowerPC 601 are trademarks of International Business Machines Corp.  
5/95  
Motorola, Inc. 1995  

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