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MPC2004

更新时间: 2024-10-28 22:46:03
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA PC
页数 文件大小 规格书
6页 88K
描述
256KB and 512KB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms

MPC2004 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:, SIP3,.1TBReach Compliance Code:unknown
风险等级:5.91JESD-609代码:e0
端子数量:3封装主体材料:PLASTIC/EPOXY
封装等效代码:SIP3,.1TB认证状态:Not Qualified
子类别:Power Management Circuits最大供电电流 (Isup):0.75 mA
表面贴装:NO端子面层:Tin/Lead (Sn/Pb)
端子节距:2.54 mm端子位置:SINGLE
Base Number Matches:1

MPC2004 数据手册

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Order this document  
by MPC2004/D  
SEMICONDUCTOR TECHNICAL DATA  
MPC2004  
MPC2005  
Advance Information  
256KB and 512KB BurstRAM  
Secondary Cache Modules for  
PowerPC PReP/CHRP Platforms  
The MPC2004 and MPC2005 are designed to provide burstable, high perfor-  
mance 256KB/512KB L2 cache for the PowerPC 60x microprocessor family in  
conformance with the PowerPC Reference Platform (PReP) and the PowerPC  
Common Hardware Reference Platform (CHRP) specifications. The modules  
are configured as 32K x 72 and 64K x 72 bits in a 182 (91 x 2) pin DIMM format.  
Each module uses four of Motorola’s 5 V 32K x 18 or 64K x 18 BurstRAMs and  
a 5 V cache tag RAM configured as 16K x 12 for tag field plus 16K x 2 for valid and  
dirty status bits.  
Bursts can be initiated with the SRAMADS signal. Subsequent burst address-  
es are generated internal to the BurstRAM by the SRAMCNTEN signal.  
Write cycles are internally self timed and are initiated by the rising edge of the  
clock (CLKx) inputs. Eight write enables are provided for byte write control.  
Presence detect pins are available for auto configuration of the cache control.  
A serial EEPROM is optional to provide more in–depth description of the  
cache module.  
Themodulefamilypinoutwillsupport5Vand3.3Vcomponentsforaclearpath  
to lower voltage and power savings. Both power supplies must be connected.  
These cache modules are plug and pin compatible with the MPC2006, a 1MB  
synchronous module also designed for the PReP and CHRP specifications.  
They are also compatible with the MPC2007 and MPC2009, 256KB and 1MB re-  
spectively, asynchronous cache modules.  
PowerPC–style Burst Counter on Chip  
Flow–Through Data I/O  
Module Requires Both 3.3 V and 5 V Power Supplies  
Multiple Clock Pins for Reduced Loading  
All Cache Data and Tag I/Os are LVTTL (3.3 V) Compatible  
Three State Outputs  
Byte Write Capability  
Fast Module Clock Rates: 66 MHz  
Fast SRAM Access Times: 10 ns for Tag RAM Match  
9 ns for Data RAM  
Decoupling Capacitors for Each Fast Static RAM  
High Quality Multi–Layer FR4 PWB With Separate Power and Ground Planes  
182 Pin Card Edge Module  
Burndy Connector, Part Number: ELF182JSC–3Z50  
BurstRAM is a trademark of Motorola.BurstRAM is a trademark of Motorola.  
PowerPC is a trademark of International Business Machines Corp.  
This document contains information on a new product. Specifications and information herein are subject to change without notice.  
5/95  
Motorola, Inc. 1995  

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