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MM74HC74J PDF预览

MM74HC74J

更新时间： 2024-01-27 13:26:26
品牌 Logo 应用领域
美国国家半导体 - NSC 触发器锁存器逻辑集成电路
页数 文件大小 规格书
4页 114K
描述
Dual D Flip-Flop with Preset and Clear

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中文翻译

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MM74HC74J 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：DIP, DIP14,.3Reach Compliance Code：unknown
风险等级：5.92JESD-30 代码：R-PDIP-T14
JESD-609代码：e0逻辑集成电路类型：D FLIP-FLOP
功能数量：2端子数量：14
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装等效代码：DIP14,.3封装形状：RECTANGULAR
封装形式：IN-LINE电源：2/6 V
认证状态：Not Qualified子类别：FF/Latches
表面贴装：NO技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL触发器类型：POSITIVE EDGE
Base Number Matches：1

MM74HC74J 数据手册

 浏览型号MM74HC74J的Datasheet PDF文件第2页浏览型号MM74HC74J的Datasheet PDF文件第3页浏览型号MM74HC74J的Datasheet PDF文件第4页 
January 1988  
MM54HC74A/MM74HC74A  
Dual D Flip-Flop with Preset and Clear  
General Description  
The MM54HC74A/MM74HC74A utilizes advanced silicon-  
gate CMOS technology to achieve operating speeds similar  
to the equivalent LS-TTL part. It possesses the high noise  
immunity and low power consumption of standard CMOS  
integrated circuits, along with the ability to drive 10 LS-TTL  
loads.  
The 54HC/74HC logic family is functionally and pinout com-  
patible with the standard 54LS/74LS logic family. All inputs  
are protected from damage due to static discharge by inter-  
nal diode clamps to V  
and ground.  
CC  
Features  
Y
This flip-flop has independent data, preset, clear, and clock  
inputs and Q and Q outputs. The logic level present at the  
data input is transferred to the output during the positive-go-  
ing transition of the clock pulse. Preset and clear are inde-  
pendent of the clock and accomplished by a low level at the  
appropriate input.  
Typical propagation delay: 20 ns  
Y
Y
Y
Y
Wide power supply range: 2–6V  
Low quiescent current: 40 mA maximum (74HC Series)  
Low input current: 1 mA maximum  
Fanout of 10 LS-TTL loads  
Connection and Logic Diagrams  
Truth Table  
Dual-In-Line Package  
Inputs  
Outputs  
PR  
CLR  
CLK  
D
Q
Q
L
H
L
H
L
X
X
X
X
X
H
L
H
L
L
H*  
H
H
H*  
L
L
X
H
H
H
H
H
H
u
u
L
L
H
X
Q0  
Q0  
e
Note: Q0 the level of Q before the indicated input condi-  
tions were established.  
* This configuration is nonstable; that is, it will not persist  
when preset and clear inputs return to their inactive (high)  
level.  
TL/F/5106–1  
Order Number MM54HC74A or MM74HC74A  
TL/F/5106–2  
C
1995 National Semiconductor Corporation  
TL/F/5106  
RRD-B30M105/Printed in U. S. A.  
1234

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