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MM74HC193N PDF预览

MM74HC193N

更新时间: 2024-11-25 13:11:39
品牌 Logo 应用领域
美国国家半导体 - NSC 计数器
页数 文件大小 规格书
8页 170K
描述
IC HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PDIP16, DIP-16, Counter

MM74HC193N 技术参数

是否Rohs认证:不符合生命周期:Obsolete
包装说明:DIP, DIP16,.3Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.21
Is Samacsys:N其他特性:TCO UP AND TCO DOWN OUTPUTS; SEPARATE UP/DOWN CLOCK
计数方向:BIDIRECTIONAL系列:HC/UH
JESD-30 代码:R-PDIP-T16JESD-609代码:e0
长度:19.305 mm负载电容(CL):50 pF
负载/预设输入:YES逻辑集成电路类型:BINARY COUNTER
最大频率@ Nom-Sup:14000000 Hz最大I(ol):0.004 A
工作模式:SYNCHRONOUS位数:4
功能数量:1端子数量:16
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:2/6 V传播延迟(tpd):69 ns
认证状态:Not Qualified座面最大高度:5.08 mm
子类别:Counters最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:7.62 mm
最小 fmax:14 MHzBase Number Matches:1

MM74HC193N 数据手册

 浏览型号MM74HC193N的Datasheet PDF文件第2页浏览型号MM74HC193N的Datasheet PDF文件第3页浏览型号MM74HC193N的Datasheet PDF文件第4页浏览型号MM74HC193N的Datasheet PDF文件第5页浏览型号MM74HC193N的Datasheet PDF文件第6页浏览型号MM74HC193N的Datasheet PDF文件第7页 
January 1988  
MM54HC192/MM74HC192  
Synchronous Decade Up/Down Counters  
MM54HC193/MM74HC193  
Synchronous Binary Up/Down Counters  
General Description  
These high speed synchronous counters utilize advanced  
silicon-gate CMOS technology to achieve the high noise im-  
munity and low power consumption of CMOS technology,  
along with the speeds of low power Schottky TTL. The  
MM54HC192/MM74HC192 is a decade counter, and the  
MM54HC193/MM74HC193 is a binary counter. Both coun-  
ters have two separate clock inputs, an UP COUNT input  
and a DOWN COUNT input. All outputs of the flip-flops are  
simultaneously triggered on the low to high transition of ei-  
ther clock while the other input is held high. The direction of  
counting is determined by which input is clocked.  
Both a BORROW and CARRY output are provided to en-  
able cascading of both up and down counting functions. The  
BORROW output produces a negative going pulse when the  
counter underflows and the CARRY outputs a pulse when  
the counter overflows. The counters can be cascaded by  
connecting the CARRY and BORROW outputs of one de-  
vice to the COUNT UP and COUNT DOWN inputs, respec-  
tively, of the next device.  
All inputs are protected from damage due to static dis-  
charge by diodes to V  
and ground.  
CC  
These counters may be preset by entering the desired data  
on the DATA A, DATA B, DATA C, and DATA D inputs.  
When the LOAD input is taken low the data is loaded inde-  
pendently of either clock input. This feature allows the count-  
ers to be used as divide-by-n counters by modifying the  
count length with the preset inputs.  
Features  
Y
Typical propagation delay,  
Count up to Q: 28 ns  
Y
Y
Y
Typical operating frequency: 27 MHz  
Wide power supply range: 26V  
Low quiescent supply current: 80 mA maximum  
(74HC Series)  
In addition both counters can also be cleared. This is ac-  
complished by inputting a high on the CLEAR input. All 4  
internal stages are set to a low level independently of either  
COUNT input.  
Y
Y
Low input current: 1 mA maximum  
4 mA output drive  
Connection Diagram  
Truth Table  
Count  
Dual-In-Line Package  
Clear  
Load  
Function  
Up  
Down  
H
u
X
L
L
H
H
X
L
Count Up  
Count Down  
Clear  
u
H
X
H
L
X
X
Load  
e
e
H
L
high level  
low level  
e
transition from low-to-high  
u
X
e
don’t care  
TL/F/5011–1  
Order Number MM54HC192/193 or MM74HC192/193  
C
1995 National Semiconductor Corporation  
TL/F/5011  
RRD-B30M115/Printed in U. S. A.  

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