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MM74HC195

更新时间： 2024-11-02 05:08:35
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美国国家半导体 - NSC 移位寄存器
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6页 160K
描述
4-Bit Parallel Shift Register

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MM74HC195 数据手册

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November 1995  
MM54HC195/MM74HC195  
4-Bit Parallel Shift Register  
General Description  
The MM54HC195/MM74HC195 is a high speed 4-bit SHIFT  
REGISTER utilizes advanced silicon-gate CMOS technolo-  
gy to achieve the low power consumption and high noise  
immunity of standard CMOS integrated circuits, along with  
the ability to drive 10 LS-TTL loads at LS type speeds.  
trol input is high. Serial data for this mode is entered at the  
J-K inputs. These inputs allow the first stage to perform as a  
J-K or TOGGLE flip flop as shown in the truth table.  
The 54HC/74HC logic family is functionally as well as pin-  
out compatible with the standard 54LS/74LS logic family.  
All inputs are protected from damage due to static dis-  
This shift register features parallel inputs, parallel outputs, J-  
K serial inputs, SHIFT/LOAD control input, and a direct  
overriding CLEAR. This shift register can operate in two  
modes: PARALLEL LOAD; SHIFT from Q towards Q .  
charge by internal diode clamps to V  
and ground.  
CC  
A
D
Features  
Y
Parallel loading is accomplished by applying the four bits of  
data, and taking the SHIFT/LOAD control input low. The  
data is loaded into the associated flip flops and appears at  
the outputs after the positive transition of the clock input.  
During parallel loading, serial data flow is inhibited. Serial  
shifting occurs synchronously when the SHIFT/LOAD con-  
Typical operating frequency: 45 MHz  
Y
Y
Y
Y
Y
Typical propagation delay: 16 ns (clock to Q)  
Wide operating supply voltage range: 2–6V  
Low input current: 1 mA maximum  
Low quiescent current: 80 mA maximum (74HC Series)  
Fanout of 10 LS-TTL loads  
Connection Diagram  
Dual-In-Line Package  
TL/F/5324–1  
Top View  
Order Number MM54HC195 or MM74HC195  
Function Table  
e
e
e
H
L
high level (steady state)  
Inputs  
Outputs  
low level (steady state)  
X
irrelevant (any input, including transitions)  
Serial  
Parallel  
Clear Shift/ Clock  
Load  
Q
Q
Q
Q
Q
D
A
B
C
D
e
transition from low to high level  
u
J
K
A
B
C
D
e
a, b, c, d  
or D, respectively.  
, Q , Q , Q  
the level of steady-state input at inputs A, B, C,  
L
X
L
X
X
X
X
L
L
H
H
X
X
X
H
L
X
a
X
b
X
c
X
d
L
a
L
b
Q
Q
Q
Q
Q
L
c
L
d
H
d
e
the level of Q , Q , Q , or Q ,  
A B C D  
H
H
H
H
H
H
Q
u
A0  
B0 C0  
D0  
H
H
H
H
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Q
Q
Q
Q
Q
respectively, before the indicated steady-state input condi-  
tions were established.  
A0  
A0  
B0  
A0  
An  
An  
An  
C0  
Bn  
Bn  
Bn  
Bn  
D0  
Cn  
Cn  
Cn  
Cn  
D0  
Cn  
Cn  
Cn  
Cn  
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
u
u
u
u
e
the level of Q , Q , Q , respectively,  
A B C  
L
H
Q
, Q , Q  
Bn  
An  
Cn  
H
L
before the most-recent transition of the clock.  
Q
An  
C
1995 National Semiconductor Corporation  
TL/F/5324  
RRD-B30M115/Printed in U. S. A.  
123456

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