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MM74HC194N PDF预览

MM74HC194N

更新时间： 2024-11-10 23:02:43
品牌 Logo 应用领域
美国国家半导体 - NSC 移位寄存器光电二极管
页数 文件大小 规格书
6页 138K
描述
4-Bit Bidirectional Universal Shift Register

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中文翻译

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MM74HC194N 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：DIP, DIP16,.3Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.26
其他特性：HOLD MODE计数方向：BIDIRECTIONAL
系列：HC/UHJESD-30 代码：R-PDIP-T16
JESD-609代码：e0长度：19.305 mm
负载电容（CL）：50 pF逻辑集成电路类型：PARALLEL IN PARALLEL OUT
最大频率@ Nom-Sup：24000000 Hz位数：4
功能数量：1端子数量：16
最高工作温度：85 °C最低工作温度：-40 °C
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：DIP封装等效代码：DIP16,.3
封装形状：RECTANGULAR封装形式：IN-LINE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：2/6 V
传播延迟（tpd）：37 ns认证状态：Not Qualified
座面最大高度：5.08 mm子类别：Shift Registers
最大供电电压 (Vsup)：6 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED触发器类型：POSITIVE EDGE
宽度：7.62 mm最小 fmax：24 MHz
Base Number Matches：1

MM74HC194N 数据手册

 浏览型号MM74HC194N的Datasheet PDF文件第2页浏览型号MM74HC194N的Datasheet PDF文件第3页浏览型号MM74HC194N的Datasheet PDF文件第4页浏览型号MM74HC194N的Datasheet PDF文件第5页浏览型号MM74HC194N的Datasheet PDF文件第6页 
November 1995  
MM54HC194/MM74HC194  
4-Bit Bidirectional Universal Shift Register  
General Description  
This 4-bit high speed bidirectional shift register utilizes ad-  
vanced silicon-gate CMOS technology to achieve the low  
power consumption and high noise immunity of standard  
CMOS integrated circuits, along with the ability to drive 10  
LS-TTL loads. This device operates at speeds similar to the  
equivalent low power Schottky part.  
Serial data for this mode is entered at the SHIFT RIGHT  
data input. When S0 is low and S1 is high, data shifts left  
synchronously and new data is entered at the SHIFT LEFT  
serial input. Clocking of the flip flops is inhibited when both  
mode control inputs are low. The mode control inputs  
should be changed only when the CLOCK input is high.  
This bidirectional shift register is designed to incorporate  
virtually all of the features a system designer may want in a  
shift register. It features parallel inputs, parallel outputs,  
right shift and left shift serial inputs, operating mode control  
inputs, and a direct overriding clear line. The register has  
four distinct modes of operation: PARALLEL (broadside)  
The 54HC/74HC logic family is functionally as well as pin-  
out compatible with the standard 54LS/74LS logic family.  
All inputs are protected from damage due to static dis-  
charge by internal diode clamps to V  
and ground.  
CC  
Features  
Y
LOAD; SHIFT RIGHT (in the direction Q toward Q );  
A D  
SHIFT LEFT; INHIBIT CLOCK (do nothing).  
Typical operating frequency: 45 MHz  
Y
Y
Y
Y
Typical propagation delay: ns (clock to Q)  
Wide operating supply voltage range: 2–6V  
Low input current: 1 mA maximum  
Low quiescent supply current: 160 mA maximum  
(74HC Series)  
Synchronous parallel loading is accomplished by applying  
the four bits of data and taking both mode control inputs, S0  
and S1, high. The data are loaded into their respective flip  
flops and appear at the outputs after the positive transition  
of the CLOCK input. During loading, serial data flow is inhib-  
ited. Shift right is accomplished synchronously with the ris-  
ing edge of the clock pulse when S0 is high and S1 is low.  
Y
Fanout of 10 LS-TTL loads  
Connection Diagram  
Dual-In Line Package  
TL/F/5323–1  
Order Number MM54HC194 or MM74HC194  
Function Table  
Inputs  
Outputs  
e
e
e
H
L
high level (steady state)  
Mode  
S1 S2  
Serial  
Parallel  
low level (steady state)  
Clear  
Clock  
Q
A
Q
Q
Q
D
B
C
Left Right A B C D  
X
irrelevant (any input, including transitions)  
e
transition from low to high level  
u
a, b, c, d  
L
X
X
H
L
X
X
H
H
H
L
X
L
X
X
X
X
X
H
L
X
X
X
H
L
X
X
X
X X X X  
X X X X Q  
L
L
Q
b
L
Q
c
L
Q
d
e
respectively.  
H
H
H
H
H
H
H
the level of steady-state input at inputs A, B, C, or D,  
A0 B0 C0 D0  
a
b
c
d
a
H
L
u
u
u
u
u
X
e
before the indicated steady-state input conditions were established.  
X X X X  
X X X X  
Q
Q
Q
Q
Q
Q
Q
Q
Q
, Q , Q , Q  
B0 C0 D0  
the level of Q , Q , Q , or Q , respectively,  
C
An  
An  
Bn  
Bn  
Cn  
Cn  
A0  
A
B
D
L
e
transition of the clock.  
H
H
L
X X X X Q  
X X X X Q  
X X X X Q  
H
L
Q
Q
, Q , Q , Q  
An Bn Cn Dn  
the most-recent  
the level of Q , Q , Q , respectively, before  
B
Bn Cn Dn  
A
C
u
L
L
Q
Q
Q
Bn Cn Dn  
Q
A0 B0 C0 D0  
X
C
1995 National Semiconductor Corporation  
TL/F/5323  
RRD-B30M115/Printed in U. S. A.  
123456

中文翻译

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MM74HC194N/B+ TI

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MM74HC195J NSC

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MM74HC195J/A+ TI

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 		IC,SHIFT REGISTER,HC-CMOS,DIP,16PIN,CERAMIC
MM74HC195M TI

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 		IC,SHIFT REGISTER,HC-CMOS,SOP,16PIN,PLASTIC
MM74HC195N NSC

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 		4-Bit Parallel Shift Register
MM74HC195N/A+ TI

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 		IC,SHIFT REGISTER,HC-CMOS,DIP,16PIN,PLASTIC
MM74HC195N/A+ NSC

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