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MM74HC194

更新时间： 2024-11-24 23:02:43
品牌 Logo 应用领域
美国国家半导体 - NSC 移位寄存器
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6页 138K
描述
4-Bit Bidirectional Universal Shift Register

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MM74HC194 数据手册

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November 1995  
MM54HC194/MM74HC194  
4-Bit Bidirectional Universal Shift Register  
General Description  
This 4-bit high speed bidirectional shift register utilizes ad-  
vanced silicon-gate CMOS technology to achieve the low  
power consumption and high noise immunity of standard  
CMOS integrated circuits, along with the ability to drive 10  
LS-TTL loads. This device operates at speeds similar to the  
equivalent low power Schottky part.  
Serial data for this mode is entered at the SHIFT RIGHT  
data input. When S0 is low and S1 is high, data shifts left  
synchronously and new data is entered at the SHIFT LEFT  
serial input. Clocking of the flip flops is inhibited when both  
mode control inputs are low. The mode control inputs  
should be changed only when the CLOCK input is high.  
This bidirectional shift register is designed to incorporate  
virtually all of the features a system designer may want in a  
shift register. It features parallel inputs, parallel outputs,  
right shift and left shift serial inputs, operating mode control  
inputs, and a direct overriding clear line. The register has  
four distinct modes of operation: PARALLEL (broadside)  
The 54HC/74HC logic family is functionally as well as pin-  
out compatible with the standard 54LS/74LS logic family.  
All inputs are protected from damage due to static dis-  
charge by internal diode clamps to V  
and ground.  
CC  
Features  
Y
LOAD; SHIFT RIGHT (in the direction Q toward Q );  
A D  
SHIFT LEFT; INHIBIT CLOCK (do nothing).  
Typical operating frequency: 45 MHz  
Y
Y
Y
Y
Typical propagation delay: ns (clock to Q)  
Wide operating supply voltage range: 2–6V  
Low input current: 1 mA maximum  
Low quiescent supply current: 160 mA maximum  
(74HC Series)  
Synchronous parallel loading is accomplished by applying  
the four bits of data and taking both mode control inputs, S0  
and S1, high. The data are loaded into their respective flip  
flops and appear at the outputs after the positive transition  
of the CLOCK input. During loading, serial data flow is inhib-  
ited. Shift right is accomplished synchronously with the ris-  
ing edge of the clock pulse when S0 is high and S1 is low.  
Y
Fanout of 10 LS-TTL loads  
Connection Diagram  
Dual-In Line Package  
TL/F/5323–1  
Order Number MM54HC194 or MM74HC194  
Function Table  
Inputs  
Outputs  
e
e
e
H
L
high level (steady state)  
Mode  
S1 S2  
Serial  
Parallel  
low level (steady state)  
Clear  
Clock  
Q
A
Q
Q
Q
D
B
C
Left Right A B C D  
X
irrelevant (any input, including transitions)  
e
transition from low to high level  
u
a, b, c, d  
L
X
X
H
L
X
X
H
H
H
L
X
L
X
X
X
X
X
H
L
X
X
X
H
L
X
X
X
X X X X  
X X X X Q  
L
L
Q
b
L
Q
c
L
Q
d
e
respectively.  
H
H
H
H
H
H
H
the level of steady-state input at inputs A, B, C, or D,  
A0 B0 C0 D0  
a
b
c
d
a
H
L
u
u
u
u
u
X
e
before the indicated steady-state input conditions were established.  
X X X X  
X X X X  
Q
Q
Q
Q
Q
Q
Q
Q
Q
, Q , Q , Q  
B0 C0 D0  
the level of Q , Q , Q , or Q , respectively,  
C
An  
An  
Bn  
Bn  
Cn  
Cn  
A0  
A
B
D
L
e
transition of the clock.  
H
H
L
X X X X Q  
X X X X Q  
X X X X Q  
H
L
Q
Q
, Q , Q , Q  
An Bn Cn Dn  
the most-recent  
the level of Q , Q , Q , respectively, before  
B
Bn Cn Dn  
A
C
u
L
L
Q
Q
Q
Bn Cn Dn  
Q
A0 B0 C0 D0  
X
C
1995 National Semiconductor Corporation  
TL/F/5323  
RRD-B30M115/Printed in U. S. A.  
123456

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