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MM54C922J/A+ PDF预览

MM54C922J/A+

更新时间: 2024-09-15 13:00:39
品牌 Logo 应用领域
美国国家半导体 - NSC 编码器
页数 文件大小 规格书
10页 220K
描述
IC,ENCODER,CMOS,DIP,18PIN,CERAMIC

MM54C922J/A+ 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP18,.3Reach Compliance Code:unknown
风险等级:5.92JESD-30 代码:R-XDIP-T18
JESD-609代码:e0逻辑集成电路类型:ENCODER
端子数量:18最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:CERAMIC
封装代码:DIP封装等效代码:DIP18,.3
封装形状:RECTANGULAR封装形式:IN-LINE
电源:5/15 V子类别:Arithmetic Circuits
表面贴装:NO技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUALBase Number Matches:1

MM54C922J/A+ 数据手册

 浏览型号MM54C922J/A+的Datasheet PDF文件第2页浏览型号MM54C922J/A+的Datasheet PDF文件第3页浏览型号MM54C922J/A+的Datasheet PDF文件第4页浏览型号MM54C922J/A+的Datasheet PDF文件第5页浏览型号MM54C922J/A+的Datasheet PDF文件第6页浏览型号MM54C922J/A+的Datasheet PDF文件第7页 
July 1993  
MM54C922/MM74C922 16-Key Encoder  
MM54C923/MM74C923 20-Key Encoder  
General Description  
These CMOS key encoders provide all the necessary logic  
to fully encode an array of SPST switches. The keyboard  
scan can be implemented by either an external clock or  
external capacitor. These encoders also have on-chip pull-  
up devices which permit switches with up to 50 kX on resist-  
ance to be used. No diodes in the switch array are needed  
to eliminate ghost switches. The internal debounce circuit  
needs only a single external capacitor and can be defeated  
by omitting the capacitor. A Data Available output goes to a  
high level when a valid keyboard entry has been made. The  
Data Available output returns to a low level when the en-  
tered key is released, even if another key is depressed. The  
Data Available will return high to indicate acceptance of the  
new key after a normal debounce period; this two-key roll-  
over is provided between any two switches.  
An internal register remembers the last key pressed even  
after the key is released. The TRI-STATE outputs provide  
for easy expansion and bus operation and are LPTTL com-  
patible.  
É
Features  
Y
50 kX maximum switch on resistance  
Y
On or off chip clock  
Y
On-chip row pull-up devices  
Y
2 key roll-over  
Y
Keybounce elimination with single capacitor  
Y
Last key register at outputs  
Y
TRI-STATE outpust LPTTL compatible  
Y
Wide supply range  
3V to 15V  
Y
Low power consumption  
Connection Diagrams  
Pin Assignment for  
Dual-In-Line Package  
Pin Assignment  
for SOIC  
Pin Assignment for  
DIP and SOIC Package  
TL/F/603714  
Top View  
TL/F/6037–1  
Order Number MM74C922  
Top View  
TL/F/6037–2  
Top View  
Order Number MM54C922 or  
MM74C922  
Order Number MM54C923 or  
MM74C923  
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.  
C
1995 National Semiconductor Corporation  
TL/F/6037  
RRD-B30M105/Printed in U. S. A.  

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