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MM54C95J PDF预览

MM54C95J

更新时间: 2024-11-05 22:46:11
品牌 Logo 应用领域
美国国家半导体 - NSC 逻辑集成电路
页数 文件大小 规格书
4页 111K
描述
4-Bit Right-Shift Left-Shift Register

MM54C95J 数据手册

 浏览型号MM54C95J的Datasheet PDF文件第2页浏览型号MM54C95J的Datasheet PDF文件第3页浏览型号MM54C95J的Datasheet PDF文件第4页 
February 1988  
MM54C95/MM74C95  
4-Bit Right-Shift Left-Shift Register  
General Description  
Features  
Y
Medium speed operation  
10 MHz (typ.)  
e
This 4-bit shift register is a monolithic complementary MOS  
(CMOS) integrated circuit composed of four D flip-flops.  
This register will perform right-shift or left-shift operations  
dependent upon the logical input level to the mode control.  
A number of these registers may be connected in series to  
form an N-bit right-shift or left-shift register.  
e
V
CC  
10V, C  
50 pF  
(typ.)  
L
Y
High noise immunity  
0.45 V  
CC  
Y
Low power  
100 nW/(typ.)  
Y
Tenth power TTL compatible  
Drive 2 LTTL loads  
3V to 15V  
Y
Wide supply voltage range  
When a logical ‘‘0’’ level is applied to the mode control in-  
put, the output of each flip-flop is coupled to the D input of  
the succeeding flip flop. Right-shift operation is performed  
by clocking at the clock 1 input, and serial data entered at  
the serial input, clock 2 and parallel inputs A through D are  
inhibited. With a logical ‘‘1’’ level applied to the mode con-  
trol, outputs to succeeding stages are decoupled and paral-  
lel loading is possible, or with external interconnection, shift-  
left operation can be accomplished by connecting the out-  
put of each flip-flop to the parallel input of the previous  
flip-flop and serial data is entered at input D.  
Y
Synchronous parallel load  
Y
Parallel inputs and outputs from each flip-flop  
Negative edge triggered clocking  
Y
Y
The MM54C95/MM74C95 follows the MM54L95/  
MM74L95 Pinout  
Applications  
Y
Y
Y
Y
Y
Data terminals  
Alarm systems  
Remote metering  
Industrial electronics  
Computers  
Y
Instrumentation  
Y
Automotive  
Y
Medical electronics  
Block and Connection Diagrams  
TL/F/5890–2  
TL/F/5890–1  
Dual-In-Line Package  
TL/F/5890–3  
e
e
Mode Control  
Mode Control  
0 for Right Shift  
1 for Left Shift or Parallel Load  
TL/F/5890–4  
Order Number MM54C95 or MM74C95  
C
1995 National Semiconductor Corporation  
TL/F/5890  
RRD-B30M105/Printed in U. S. A.  

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