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MM54HC03 PDF预览

MM54HC03

更新时间: 2024-11-06 04:39:35
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美国国家半导体 - NSC
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4页 129K
描述
Open Drain NAND Gate

MM54HC03 数据手册

 浏览型号MM54HC03的Datasheet PDF文件第2页浏览型号MM54HC03的Datasheet PDF文件第3页浏览型号MM54HC03的Datasheet PDF文件第4页 
January 1988  
MM54HC03/MM74HC03 Quad 2-Input  
Open Drain NAND Gate  
General Description  
Features  
Y
Typical propagation delay: 12 ns  
These NAND gates utilize advanced silicon-gate CMOS  
technology to achieve operating speeds similar to LS-TTL  
gates with the low power consumption of standard CMOS  
integrated circuits. All gates have buffered outputs. All de-  
vices have high noise immunity and the ability to drive 10  
LS-TTL loads. The 54HC/74HC logic family is functionally  
as well as pin-out compatible with the standard 54LS/74LS  
logic family. All inputs are protected from damage due to  
Y
Wide power supply range: 26V  
Y
Low quiescent current: 20 mA maximum (74HC Series)  
Low input current: 1 mA maximum  
Y
Y
Fanout of 10 LS-TTL loads  
static discharge by internal diode clamps to  
ground.  
V
CC  
and  
As with standard 54HC/74HC push-pull outputs there are  
diodes to both V and ground. Therefore the output should  
as it would be clamped to one  
CC  
not be pulled above V  
CC  
diode voltage above V . This diode is added to enhance  
CC  
electrostatic protection.  
Connection and Logic Diagrams  
Dual-In-Line Package  
TL/F/5295–1  
Top View  
Order Number MM54HC03 or MM74HC03  
TL/F/5295–2  
C
1995 National Semiconductor Corporation  
TL/F/5295  
RRD-B30M105/Printed in U. S. A.  

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