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MCM6729WJ10 PDF预览

MCM6729WJ10

更新时间: 2024-11-10 22:26:23
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 存储
页数 文件大小 规格书
8页 149K
描述
256K x 4 Bit Fast Static Random Access Memory

MCM6729WJ10 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:0.400 INCH, PLASTIC, SOJ-32Reach Compliance Code:unknown
ECCN代码:3A991.B.2.BHTS代码:8542.32.00.41
风险等级:5.88最长访问时间:10 ns
I/O 类型:COMMONJESD-30 代码:R-PDSO-J32
JESD-609代码:e0长度:20.96 mm
内存密度:1048576 bit内存集成电路类型:STANDARD SRAM
内存宽度:4功能数量:1
端口数量:1端子数量:32
字数:262144 words字数代码:256000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:256KX4
输出特性:3-STATE可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:SOJ
封装等效代码:SOJ32,.44封装形状:RECTANGULAR
封装形式:SMALL OUTLINE并行/串行:PARALLEL
电源:5 V认证状态:Not Qualified
座面最大高度:3.75 mm子类别:SRAMs
最大压摆率:0.165 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:BICMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:J BEND端子节距:1.27 mm
端子位置:DUAL宽度:10.16 mm
Base Number Matches:1

MCM6729WJ10 数据手册

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Order this document  
by MCM6729/D  
SEMICONDUCTOR TECHNICAL DATA  
MCM6729  
256K x 4 Bit Fast Static Random  
Access Memory  
The MCM6729 is a 1,048,576 bit static random access memory organized as  
262,144wordsof4bits. Thisdeviceisfabricatedusinghighperformancesilicon–  
gate BiCMOS technology. Static design eliminates the need for external clocks  
or timing strobes.  
WJ PACKAGE  
400 MIL SOJ  
CASE 857A–02  
Output enable (G) is a special control feature that provides increased system  
flexibility and eliminates bus contention problems.  
This device meets JEDEC standards for functionality and revolutionary pinout,  
and is available in a 400 mil plastic small–outline J–leaded package.  
PIN ASSIGNMENT  
Single 5 V ± 10% Power Supply  
NC  
A
1
2
32  
Fully Static — No Clock or Timing Strobes Necessary  
All Inputs and Outputs Are TTL Compatible  
Three State Outputs  
Fast Access Times: 10, 12 ns  
Center Power and I/O Pins for Reduced Noise  
A
A
A
31  
30  
29  
28  
27  
A
3
A
A
4
A
A
5
E
G
6
DQ0  
DQ3  
VSS  
VCC  
DQ2  
A
7
26  
25  
24  
23  
BLOCK DIAGRAM  
V
8
CC  
V
9
SS  
A
A
A
DQ1  
W
10  
V
CC  
VSS  
11  
22  
21  
20  
19  
18  
17  
A
A
12  
13  
14  
15  
16  
A
MEMORY  
A
A
A
ROW  
DECODER  
MATRIX  
512 ROWS x 512 x 4  
COLUMNS  
A
A
A
A
A
A
A
A
NC  
NC  
PIN NAMES  
DQ0  
COLUMN I/O  
INPUT  
DATA  
CONTROL  
COLUMN DECODER  
A0 – A17 . . . . . . . . . . . . . . Address Input  
E . . . . . . . . . . . . . . . . . . . . . . Chip Enable  
W . . . . . . . . . . . . . . . . . . . . Write Enable  
G . . . . . . . . . . . . . . . . . . . Output Enable  
DQ0 – DQ3 . . . . . . . . Data Input/Output  
DQ3  
E
A
A
A
A
A
A
A
A
A
V
V
. . . . . . . . . . . . + 5 V Power Supply  
. . . . . . . . . . . . . . . . . . . . . . . Ground  
CC  
SS  
NC . . . . . . . . . . . . . . . . . . No Connection  
W
G
REV 4  
5/95  
Motorola, Inc. 1995  

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