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MCM67A618B PDF预览

MCM67A618B

更新时间： 2024-11-10 22:22:27
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA /
页数 文件大小 规格书
12页 145K
描述
64K x 18 Bit Asynchronous/ Latched Address Fast Static RAM

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MCM67A618B 数据手册

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Order this document  
by MCM67A618B/D  
SEMICONDUCTOR TECHNICAL DATA  
MCM67A618B  
Advance Information  
64K x 18 Bit Asynchronous/  
Latched Address Fast Static RAM  
The MCM67A618B is a 1,179,648 bit latched address static random access  
memory organized as 65,536 words of 18 bits. The device integrates a 64K x 18  
SRAM core with advanced peripheral circuitry consisting of address and data in-  
put latches, active low chip enable, separate upper and lower byte write strobes,  
and a fast output enable. This device has increased output drive capability sup-  
ported by multiple power pins.  
FN PACKAGE  
PLASTIC  
CASE 778–02  
Address, data in, and chip enable latches are provided. When latch enables  
(AL for address and chip enables and DL for data in) are high, the address, data  
in, and chip enable latches are in the transparent state. If latch enables are tied  
high the device can be used as an asynchronous SRAM. When latch enables are  
low the address, data in, and chip enable latches are in the latched state. This  
input latch simplifies read and write cycles by guaranteeing address and data–in  
hold time in a simple fashion.  
PIN ASSIGNMENT  
7
6
5
4
3
2
1
52 51 50 49 48 47  
46  
DQ8  
DQ7  
DQ6  
DQ9  
8
9
Dual write enables (LW and UW) are provided to allow individually  
writeable bytes. LW controls DQ0 – DQ8 (the lower bits) while UW  
controls DQ9 – DQ17 (the upper bits).  
Six pair of power and ground pins have been utilized and placed on  
the package for maximum performance.  
The MCM67A618B will be available in a 52–pin plastic leaded chip  
45  
44  
43  
DQ10  
V
V
10  
11  
CC  
SS  
V
CC  
42  
41  
40  
DQ11  
DQ12  
12  
13  
14  
V
SS  
DQ5  
DQ4  
DQ13  
carrier (PLCC).  
39  
38  
DQ14  
15  
16  
DQ3  
DQ2  
This device is ideally suited for systems that require wide data bus  
widths, cache memory, and tag RAMs.  
V
SS  
37  
36  
35  
34  
V
17  
18  
19  
V
CC  
SS  
DQ15  
DQ16  
V
DQ1  
DQ0  
CC  
•
•
•
•
•
•
•
•
•
Single 5 V ± 5% Power Supply  
Fast Access Times: 10/12/15 ns Max  
Byte Writeable via Dual Write Enables  
Separate Data Input Latch for Simplified Write Cycles  
Address and Chip Enable Input Latches  
Common Data Inputs and Data Outputs  
Output Enable Controlled Three–State Outputs  
3.3 V I/O Compatible  
DQ17  
20  
21 22 23 24 25 26 27 28 29 30 31 32 33  
PIN NAMES  
A0 – A15 . . . . . . . . . . . . . . . . Address Inputs  
AL . . . . . . . . . . . . . . . . . . . . . . Address Latch  
DL . . . . . . . . . . . . . . . . . . . . . . . . . Data Latch  
LW . . . . . . . . . . . . Lower Byte Write Enable  
UW . . . . . . . . . . . . Higher Byte Write Enable  
E . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable  
G . . . . . . . . . . . . . . . . . . . . . . Output Enable  
DQ0 – DQ17 . . . . . . . . . . . Data Input/Output  
High Board Density 52–Lead PLCC Package  
V
CC  
V
SS  
. . . . . . . . . . . . . . . . + 5 V Power Supply  
. . . . . . . . . . . . . . . . . . . . . . . . . . . Ground  
Allpowersupplyandgroundpinsmustbecon-  
nected for proper operation of the device.  
This document contains information on a new product. Specifications and information herein are subject to change without notice.  
REV 2  
7/16/97  
Motorola, Inc. 1997  
1234567...12

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MCM67A618FN12 MOTOROLA

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