Datasheet > MCM67B518

MCM67B518

更新时间： 2024-11-10 22:22:31

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		/
页数	文件大小	规格书
12页	210K
描述
32K x 18 Bit BurstRAM Synchronous Fast Static RAM

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MCM67B518 数据手册

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SEMICONDUCTOR TECHNICAL DATA

MCM67B518

32K x 18 Bit BurstRAM

Synchronous Fast Static RAM

With Burst Counter and Self–Timed Write

The MCM67B518 is a 589,824 bit synchronous fast static random access

memory designed to provide a burstable, high–performance, secondary cache

for the i486 and Pentium microprocessors. It is organized as 32,768 words

of 18 bits, fabricated with Motorola’s high–performance silicon–gate BiCMOS

technology. The device integrates input registers, a 2–bit counter, high speed

SRAM, and high drive capability outputs onto a single monolithic circuit for re-

duced parts count implementation of cache data RAM applications. Synchro-

nous design allows precise cycle control with the use of an external clock (K).

BiCMOS circuitry reduces the overall power consumption of the integrated func-

tions for greater reliability.

FN PACKAGE

PLASTIC

CASE 778–02

PIN ASSIGNMENTS

Addresses (A0 – A14), data inputs (D0 – D17), and all control signals except

output enable (G) are clock (K) controlled through positive–edge–triggered

noninverting registers.

1 52 51 50 49 48 47

Bursts canbeinitiatedwitheitheraddressstatusprocessor(ADSP) or address

status cache controller (ADSC) input pins. Subsequent burst addresses can be

generated internally by the MCM67B518 (burst sequence imitates that of the

i486 and Pentium) and controlled by the burst address advance (ADV) input pin.

The following pages provide more detailed information on burst controls.

Write cycles are internally self–timed and are initiated by the rising edge of the

clock (K) input. This feature eliminates complex off–chip write pulse generation

and provides increased flexibility for incoming signals.

Dual write enables (LW and UW) are provided to allow individually writeable

bytes. LW controls DQ0 – DQ8 (the lower bits), while UW controls DQ9 – DQ17

(the upper bits).

This device is ideally suited for systems that require wide data bus widths and

cache memory. See Figure 2 for applications information.

DQ9

DQ10

DQ8

DQ7

DQ6

DQ12

DQ11

DQ13

DQ14

DQ5

DQ4

DQ3

DQ2

DQ15

DQ16

DQ17

DQ1

DQ0

21 22 23 24 25 26 27 28 29 30 31 32 33

•

Single 5 V ± 5% Power Supply

Fast Access Times: 9/10/12 ns Max

Byte Writeable via Dual Write Enables

Internal Input Registers (Address, Data, Control)

Internally Self–Timed Write Cycle

ADSP, ADSC, and ADV Burst Control Pins

Asynchronous Output Enable Controlled Three–State Outputs

Common Data Inputs and Data Outputs

3.3 V I/O Compatible

PIN NAMES

A0 – A14 . . . . . . . . . . . . . . . . Address Inputs

K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock

ADV . . . . . . . . . . . . . Burst Address Advance

LW . . . . . . . . . . . . . Lower Byte Write Enable

UW . . . . . . . . . . . . . Upper Byte Write Enable

ADSC . . . . . . . . . Controller Address Status

ADSP . . . . . . . . . . Processor Address Status

E . . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable

G . . . . . . . . . . . . . . . . . . . . . . . Output Enable

DQ0 – DQ17 . . . . . . . . . . . Data Input/Output

High Board Density 52–Lead PLCC Package

. . . . . . . . . . . . . . . . + 5 V Power Supply

. . . . . . . . . . . . . . . . . . . . . . . . . . . Ground

NC . . . . . . . . . . . . . . . . . . . . . . No Connection

All power supply and ground pins must be

connected for proper operation of the device.

BurstRAM is a trademark of Motorola, Inc.

i486 and Pentium are trademarks of Intel Corp.

REV 2

5/95

Motorola, Inc. 1994

MOTOROLA FAST SRAM

MCM67B518

12 3 4 5 6 7...12

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与MCM67B518相关器件

型号	品牌	获取价格	描述	数据表
MCM67B518AFN8.5	MOTOROLA	获取价格	32KX18 CACHE SRAM, 8.5ns, PQCC52, PLASTIC, LCC-52
MCM67B518AZP9	MOTOROLA	获取价格	32KX18 CACHE SRAM, 9ns, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-119
MCM67B518FN10	MOTOROLA	获取价格	32K x 18 Bit BurstRAM Synchronous Fast Static RAM
MCM67B518FN12	MOTOROLA	获取价格	32K x 18 Bit BurstRAM Synchronous Fast Static RAM
MCM67B518FN18	MOTOROLA	获取价格	32K X 18 CACHE SRAM, 18 ns, PQCC52, PLASTIC, LCC-52
MCM67B518FN9	MOTOROLA	获取价格	32K x 18 Bit BurstRAM Synchronous Fast Static RAM
MCM67B518ZP10	MOTOROLA	获取价格	Memory IC
MCM67B518ZP9	MOTOROLA	获取价格	Memory IC
MCM67B618A	MOTOROLA	获取价格	64K x 18 Bit BurstRAM Synchronous Fast Static RAM
MCM67B618AFN10	MOTOROLA	获取价格	64K x 18 Bit BurstRAM Synchronous Fast Static RAM

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