Datasheet > MCM67B618B

MCM67B618B

更新时间： 2024-11-08 04:40:27

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		计数器
页数	文件大小	规格书
11页	110K
描述
64K x 18 Bit BurstRAM Synchronous Fast Static RAM With Burst Counter and Self-Timed Write

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MCM67B618B 数据手册

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

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MCM67B618B

Advance Information

64K x 18 Bit BurstRAM

Synchronous Fast Static RAM

With Burst Counter and Self–Timed Write

The MCM67B618B is a 1,179,648–bit synchronous fast static random access

memory designed to provide a burstable, high–performance, secondary cache

for the i486 and Pentiumr microprocessors. The MCM67B618B (organized as

65,536 words by 18 bits) is fabricated using Motorola’s high–performance

silicon–gate BiCMOS technology. The device integrates input registers, a 2–bit

counter, high speed SRAM, and high drive capability outputs onto a single

monolithic circuit for reduced parts count implementation of cache data RAM

applications. Synchronous design allows precise cycle control with the use of an

external clock (K). BiCMOS circuitry reduces the overall power consumption of

the integrated functions for greater reliability.

FN PACKAGE

PLASTIC

CASE 778–02

PIN ASSIGNMENTS

Addresses (A0 – A15), data inputs (D0 – D17), and all control signals

except output enable (G) are clock (K) controlled through positive–

edge–triggered noninverting registers.

Bursts can be initiated with either address status processor (ADSP)

or address status cache controller (ADSC) input pins. Subsequent

burst addresses can be generated internally by the MCM67B618B

(burst sequence imitates that of the i486 and Pentium) and controlled

by the burst address advance (ADV) input pin. The following pages pro-

vide more detailed information on burst controls.

Write cycles are internally self–timed and are initiated by the rising

edge of the clock (K) input. This feature eliminates complex off–chip

write pulse generation and provides increased flexibility for incoming

signals.

Dual write enables (LW and UW) are provided to allow individually

writeable bytes. LW controls DQ0 – DQ8 (the lower bits), while UW

controls DQ9 – DQ17 (the upper bits).

1 52 51 50 49 48 47

DQ9

DQ8

DQ10

DQ7

DQ6

DQ11

DQ12

DQ5

DQ4

DQ3

DQ2

DQ13

DQ14

DQ15

DQ16

DQ17

DQ1

DQ0

21 22 23 24 25 26 27 28 29 30 31 32 33

This device is ideally suited for systems that require wide data bus

widths and cache memory. See Figure 2 for applications information.

•

Single 5 V ±5% Power Supply

Fast Access Time: 9 ns Max

PIN NAMES

Byte Writeable via Dual Write Enables

Internal Input Registers (Address, Data, Control)

Internally Self–Timed Write Cycle

ADSP, ADSC, and ADV Burst Control Pins

Asynchronous Output Enable Controlled Three–State Outputs

Common Data Inputs and Data Outputs

3.3 V I/O Compatible

A0 – A15 . . . . . . . . . . . . . . . . Address Inputs

K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock

ADV . . . . . . . . . . . . Burst Address Advance

LW . . . . . . . . . . . . Lower Byte Write Enable

UW . . . . . . . . . . . . Upper Byte Write Enable

ADSC . . . . . . . . . Controller Address Status

ADSP . . . . . . . . . Processor Address Status

E . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable

G . . . . . . . . . . . . . . . . . . . . . . Output Enable

DQ0 – DQ17 . . . . . . . . . . Data Input/Output

High Board Density 52–Lead PLCC Package

. . . . . . . . . . . . . . . . +5 V Power Supply

. . . . . . . . . . . . . . . . . . . . . . . . . . Ground

NC . . . . . . . . . . . . . . . . . . . . . No Connection

All power supply and ground pins must be con-

nected for proper operation of the device.

i486 is a trademark and Pentium is a registered trademark of Intel Corp.

This document contains information on a new product. Specifications and information herein are subject to change without notice.

REV 3

9/21/99

Motorola, Inc. 1999

MOTOROLA FAST SRAM

MCM67B618B

12 3 4 5 6 7...11

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与MCM67B618B相关器件

型号	品牌	获取价格	描述	数据表
MCM67B618BFN10	MOTOROLA	获取价格	64KX18 CACHE SRAM, 10ns, PQCC52, PLASTIC, LCC-52
MCM67B618BFN12	MOTOROLA	获取价格	Cache SRAM, 64KX18, 12ns, BICMOS, PQCC52, PLASTIC, LCC-52
MCM67B618BFN9	MOTOROLA	获取价格	64K x 18 Bit BurstRAM Synchronous Fast Static RAM With Burst Counter and Self-Timed Write
MCM67B618BFN9R	MOTOROLA	获取价格	64KX18 CACHE SRAM, 9ns, PQCC52, PLASTIC, LCC-52
MCM67B618FN12	MOTOROLA	获取价格	Cache SRAM, 64KX18, 12ns, BICMOS, PQCC52, PLASTIC, LCC-52
MCM67C518	MOTOROLA	获取价格	32K x 18 Bit BurstRAM Synchronous Fast Static RAM
MCM67C518AFN5	MOTOROLA	获取价格	32KX18 CACHE SRAM, 5ns, PQCC52, PLASTIC, LCC-52
MCM67C518AFN7	MOTOROLA	获取价格	32KX18 CACHE SRAM, 7ns, PQCC52, PLASTIC, LCC-52
MCM67C518AFN9	MOTOROLA	获取价格	Memory IC
MCM67C518AZP9	MOTOROLA	获取价格	Memory IC

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