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MCM67C618BFN7R

更新时间： 2024-09-18 13:11:23
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 存储内存集成电路静态存储器信息通信管理
页数 文件大小 规格书
12页 205K
描述
64KX18 CACHE SRAM, 7ns, PQCC52, PLASTIC, LCC-52

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MCM67C618BFN7R 技术参数

生命周期：Obsolete零件包装代码：LCC
包装说明：QCCJ,针数：52
Reach Compliance Code：unknownECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.84
Is Samacsys：N最长访问时间：7 ns
JESD-30 代码：S-PQCC-J52长度：19.1262 mm
内存密度：1179648 bit内存集成电路类型：CACHE SRAM
内存宽度：18功能数量：1
端口数量：1端子数量：52
字数：65536 words字数代码：64000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：64KX18
输出特性：3-STATE可输出：YES
封装主体材料：PLASTIC/EPOXY封装代码：QCCJ
封装形状：SQUARE封装形式：CHIP CARRIER
并行/串行：PARALLEL认证状态：Not Qualified
座面最大高度：4.57 mm最大供电电压 (Vsup)：5.25 V
最小供电电压 (Vsup)：4.75 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：BICMOS
温度等级：COMMERCIAL端子形式：J BEND
端子节距：1.27 mm端子位置：QUAD
宽度：19.1262 mmBase Number Matches：1

MCM67C618BFN7R 数据手册

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Order this document  
by MCM67C618B/D  
SEMICONDUCTOR TECHNICAL DATA  
MCM67C618B  
Product Preview  
64K x 18 Bit BurstRAM  
Synchronous Fast Static RAM  
With Burst Counter and Registered Outputs  
The MCM67C618B is a 1,179,648 bit synchronous static random access  
memory designed to provide a burstable, high–performance, secondary cache  
for the i486 and Pentium microprocessors. It is organized as 65,536 words  
of 18 bits, fabricated with Motorola’s high–performance silicon–gate BiCMOS  
technology. The device integrates input registers, a 2–bit counter, high speed  
SRAM, and high drive registered output drivers onto a single monolithic circuit  
for reduced parts count implementation of cache data RAM applications. Syn-  
chronousdesignallowsprecisecyclecontrolwiththeuseofanexternalclock(K).  
BiCMOS circuitry reduces the overall power consumption of the integrated  
functions for greater reliability.  
FN PACKAGE  
PLASTIC  
CASE 778–02  
PIN NAMES  
A0 – A15 . . . . . . . . . . . . . . . . Address Inputs  
K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock  
ADV . . . . . . . . . . . . Burst Address Advance  
LW . . . . . . . . . . . . Lower Byte Write Enable  
UW . . . . . . . . . . . . Upper Byte Write Enable  
ADSC . . . . . . . . . Controller Address Status  
ADSP . . . . . . . . . Processor Address Status  
E . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable  
G . . . . . . . . . . . . . . . . . . . . . . Output Enable  
DQ0 – DQ17 . . . . . . . . . . Data Input/Output  
Addresses (A0 – A15), data inputs (D0 – D17), and all control signals except  
output enable (G) are clock (K) controlled through positive–edge–triggered non-  
inverting registers.  
This device contains output registers for pipeline operations. At the rising edge  
of K, the RAM provides the output data from the previous cycle.  
Output enable (G) is asynchronous for maximum system design flexibility.  
Burst can be initiated with either address status processor (ADSP) or address  
status cache controller (ADSC) input pins. Subsequent burst addresses can be  
generated internally by the MCM67C618B (burst sequence imitates that of the  
i486 and Pentium) and controlled by the burst address advance (ADV) input pin.  
The following pages provide more detailed information on burst controls.  
Write cycles are internally self–timed and are initiated by the rising edge of the  
clock (K) input. This feature eliminates complex off–chip write pulse generation  
and provides increased flexibility for incoming signals.  
V
CC  
V
SS  
. . . . . . . . . . . . . . . . + 5 V Power Supply  
. . . . . . . . . . . . . . . . . . . . . . . . . . Ground  
NC . . . . . . . . . . . . . . . . . . . . . No Connection  
All power supply and ground pins must be  
connected for proper operation of the device.  
Dual write enables (LW and UW) are provided to allow individually writeable  
bytes. LW controls DQ0 – DQ8 (the lower bits), while UW controls DQ9 – DQ17  
(the upper bits).  
PIN ASSIGNMENT  
This device is ideally suited for systems that require wide data bus widths and  
cache memory. See Figure 2 for applications information.  
7
6
5
4
3
2
1 52 51 50 49 48 47  
46  
•
•
•
•
•
•
•
•
•
•
•
Single 5 V ± 5% Power Supply  
Fast Access Time/Fast Cycle Time = 5 ns/100 MHz, 7 ns/80 MHz  
Byte Writeable via Dual Write Enables  
Internal Input Registers (Address, Data, Control)  
Output Registers for Pipelined Applications  
Internally Self–Timed Write Cycle  
ADSP, ADSC, and ADV Burst Control Pins  
Asynchronous Output Enable Controlled Three–State Outputs  
Common Data Inputs and Data Outputs  
3.3 V I/O Compatible  
8
9
DQ9  
DQ10  
DQ8  
DQ7  
DQ6  
45  
44  
43  
V
V
10  
CC  
SS  
11  
V
CC  
DQ11  
DQ12  
DQ13  
12  
13  
14  
42  
41  
40  
V
DQ5  
DQ4  
SS  
DQ14  
15  
16  
17  
18  
19  
20  
39  
38  
37  
36  
35  
34  
DQ3  
DQ2  
V
SS  
V
V
CC  
SS  
DQ15  
DQ16  
DQ17  
V
CC  
DQ1  
DQ0  
High Board Density 52–Lead PLCC Package  
21 22 23 24 25 26 27 28 29 30 31 32 33  
BurstRAM is a trademark of Motorola, Inc.  
i486 and Pentium are trademarks of Intel Corp.  
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.  
7/96  
Motorola, Inc. 1996  
1234567...12

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