Datasheet > MCM63R818RS4.4

MCM63R818RS4.4

更新时间： 2024-09-18 03:27:55

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		静态存储器
页数	文件大小	规格书
21页	311K
描述
256KX18 LATE-WRITE SRAM, 2.2ns, CBGA119, FLIP CHIP, CERAMIC, BGA-119

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

MCM63R818RS4.4 数据手册

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Order this document

by MCM63R736/D

MCM63R736

MCM63R818

4M Late Write HSTL

The MCM63R736/818 is a 4M–bit synchronous late write fast static RAM

designed to provide high performance in secondary cache and ATM switch,

Telecom, and other high speed memory applications. The MCM63R818

(organized as 256K words by 18 bits), and the MCM63R736 (organized as 128K

words by 36 bits) are fabricated in Motorola’s high performance silicon gate

copper CMOS technology.

The differential clock (CK) inputs control the timing of read/write operations of

theRAM. AttherisingedgeofCK, alladdresses, writeenables, andsynchronous

selects are registered. An internal buffer and special logic enable the memory to

accept write data on the rising edge of CK, a cycle after address and control sig-

nals. Read data is also driven on the rising edge of CK.

FC PACKAGE

FLIPPED CHIP PBGA

CASE 999E–01

The RAM uses HSTL inputs and outputs. The adjustable input trip–point (V

)

ref

and output voltage (V

) gives the system designer greater flexibility in

DDQ

optimizing system performance.

The synchronous write and byte enables allow writing to individual bytes or the

entire word.

The impedance of the output buffers is programmable, allowing the outputs to

match the impedance of the circuit traces which reduces signal reflections.

•

Byte Write Control

2.5 V –5% to 3.3 V +10% Operation

2.375 V to 3.6 V Operation

HSTL — I/O (JEDEC Standard JESD8–6 Class I Compatible)

HSTL — User Selectable Input Trip–Point

HSTL — Compatible Programmable Impedance Output Drivers

Boundary Scan (JTAG) IEEE 1149.1 Compatible

Differential Clock Inputs

Optional x18 or x36 Organization

MCM63R736/818–3 = 3 ns

MCM63R736/818–3.3 = 3.3 ns

MCM63R736/818–3.7 = 3.7 ns

MCM63R736/818–4 = 4 ns

MCM63R736/818–4.4 = 4.4 ns

MCM63R736/818–5 = 5 ns

•

Sleep Mode Operation (ZZ pin)

119–Bump, 50 mil (1.27 mm) Pitch, 14mm x 22mm Flipped Chip Plastic

Ball Grid Array (PBGA) Package

8/6/99

Motorola, Inc. 1999

MOTOROLA FAST SRAM

MCM63R736•MCM63R818

12 3 4 5 6 7...21

中文翻译

下载PDF

与MCM63R818RS4.4相关器件

型号	品牌	获取价格	描述	数据表
MCM63R818RS4.4R	MOTOROLA	获取价格	Late-Write SRAM, 256KX18, 2.2ns, CMOS, CBGA119, FLIP CHIP, CERAMIC, BGA-119
MCM63R818RS5	MOTOROLA	获取价格	Late-Write SRAM, 256KX18, 2.5ns, CMOS, CBGA119, FLIP CHIP, CERAMIC, BGA-119
MCM63R836	FREESCALE	获取价格	MCM63R836
MCM63R836A	FREESCALE	获取价格	8M Late Write HSTL
MCM63R836AFC3.0R	MOTOROLA	获取价格	256KX36 LATE-WRITE SRAM, 1.5ns, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-119
MCM63R836AFC3.0R	NXP	获取价格	256KX36 LATE-WRITE SRAM, 1.5ns, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-119
MCM63R836AFC3.3	NXP	获取价格	IC,SYNC SRAM,256KX36,CMOS,BGA,119PIN,PLASTIC
MCM63R836AFC3.3R	NXP	获取价格	256KX36 LATE-WRITE SRAM, 1.65ns, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-119
MCM63R836AFC3.7R	NXP	获取价格	256KX36 LATE-WRITE SRAM, 1.85ns, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-119
MCM63R836AFC4.0	MOTOROLA	获取价格	256KX36 LATE-WRITE SRAM, 2ns, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-119

与MCM63R818RS4.4相关文章

摩尔斯微电子在美国约书亚树国家公园测试 Wi-Fi HaLow
2024-09-18

14
贸泽上架Tallysman TW5386智能GNSS天线
2024-09-18

13
SL74HC10N：高性能三输入与非门解析
2024-09-03

93
AIC1781A 电池充电控制器深度解析
2024-09-03

82

产品中心

服务支持

精选活动

关于我们

帮助中心

MCM63R818RS4.4

MCM63R818RS4.4 数据手册

与MCM63R818RS4.4相关器件

与MCM63R818RS4.4相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

MCM63R818RS4.4

MCM63R818RS4.4 数据手册

与MCM63R818RS4.4相关器件

与MCM63R818RS4.4相关文章

您还可以找

您在本页遇到什么问题？