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MCM63R836RS4.0 PDF预览

MCM63R836RS4.0

更新时间: 2024-11-26 04:55:59
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 静态存储器
页数 文件大小 规格书
21页 253K
描述
256KX36 LATE-WRITE SRAM, 2ns, CBGA119, 14 X 22 MM, 1.27 MM PITCH, CERAMIC, FLIP CHIP, BGA-119

MCM63R836RS4.0 数据手册

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Order this document  
by MCM63R836/D  
SEMICONDUCTOR TECHNICAL DATA  
MCM63R836  
MCM63R918  
8M Late Write HSTL  
The MCM63R836/918 is an 8M–bit synchronous late write fast static RAM  
designed to provide high performance in secondary cache and ATM switch,  
Telecom, and other high speed memory applications. The MCM63R918  
(organized as 512K words by 18 bits) and the MCM63R836 (organized as 256K  
words by 36 bits) are fabricated in Motorola’s high performance silicon gate  
CMOS technology.  
The differential clock (CK) inputs control the timing of read/write operations of  
theRAM. AttherisingedgeofCK;alladdresses, writeenables, andsynchronous  
selects are registered. An internal buffer and special logic enable the memory to  
accept write data on the rising edge of CK, a cycle after address and control  
signals. Read data is also driven on the rising edge of CK.  
FC PACKAGE  
PBGA  
CASE 999D–01  
The RAM uses HSTL inputs and outputs. The adjustable input trip–point (V  
)
ref  
and output voltage (V  
) gives the system designer greater flexibility in  
DDQ  
optimizing system performance.  
The synchronous write and byte enables allow writing to individual bytes or the  
entire word.  
RS PACKAGE  
CBGA  
The impedance of the output buffers is programmable, allowing the outputs to  
match the impedance of the circuit traces which reduces signal reflections.  
CASE 999B–01  
Byte Write Control  
2.5 V – 5% to 3.3 V + 10% Operation  
HSTL — I/O (JEDEC Standard JESD8–6 Class I Compatible)  
HSTL — User Selectable Input Trip–Point  
HSTL — Compatible Programmable Impedance Output Drivers  
Register to Register Synchronous Operation  
Boundary Scan (JTAG) IEEE 1149.1 Compatible  
Differential Clock Inputs  
Optional x18 or x36 Organization  
MCM63R836/918–3.0 = 3.0 ns  
MCM63R836/918–3.3 = 3.3 ns  
MCM63R836/918–3.7 = 3.7 ns  
MCM63R836/918–4.0 = 4.0 ns  
MCM63R836/918–4.4 = 4.4 ns  
Sleep Mode Operation (ZZ pin)  
119–Bump, 50 mil (1.27 mm) Pitch, 14 mm x 22 mm Flipped Chip Plastic  
Ball Grid Array (PBGA) or Flipped Chip Ceramic Ball Grid Array (CBGA)  
Packages  
5/3/99  
Motorola, Inc. 1999  

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