MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MCM63R836A/D
MCM63R836A
MCM63R918A
8M Late Write HSTL
The MCM63R836A/918A is an 8M–bit synchronous late write fast static RAM
designed to provide high performance in secondary cache and ATM switch,
Telecom, and other high speed memory applications. The MCM63R918A
(organized as 512K words by 18 bits) and the MCM63R836A (organized as
256K words by 36 bits) are fabricated in Motorola’shighperformancesilicongate
copper CMOS technology.
The differential clock (CK) inputs control the timing of read/write operations of
theRAM. AttherisingedgeofCK, alladdresses, writeenables, andsynchronous
selects are registered. An internal buffer and special logic enable the memory to
accept write data on the rising edge of CK, a cycle after address and control
signals. Read data is also driven on the rising edge of CK.
FC PACKAGE
PBGA
CASE 999D–01
The RAM uses HSTL inputs and outputs. The adjustable input trip–point (V
)
ref
and output voltage (V
) gives the system designer greater flexibility in
DDQ
optimizing system performance.
The synchronous write and byte enables allow writing to individual bytes or
the entire word.
The impedance of the output buffers is programmable, allowing the outputs to
match the impedance of the circuit traces which reduces signal reflections.
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Byte Write Control
2.5 V – 5% to 3.3 V + 10% Operation
HSTL — I/O (JEDEC Standard JESD8–6 Class I Compatible)
HSTL — User Selectable Input Trip–Point
HSTL — Compatible Programmable Impedance Output Drivers
Register to Register Synchronous Operation
Boundary Scan (JTAG) IEEE 1149.1 Compatible
Differential Clock Inputs
Optional x18 or x36 Organization
MCM63R836A/918A–3.0 = 3.0 ns
MCM63R836A/918A–3.3 = 3.3 ns
MCM63R836A/918A–3.7 = 3.7 ns
MCM63R836A/918A–4.0 = 4.0 ns
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Sleep Mode Operation (ZZ pin)
119–Bump, 50 mil (1.27 mm) Pitch, 14 mm x 22 mm Flipped Chip Plastic
Ball Grid Array (PBGA)
10/16/00
Motorola, Inc. 2000
MOTOROLA FAST SRAM
MCM63R836A•MCM63R918A
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