Datasheet > 存储 > SRAM> MCM63P818TQ100R

MCM63P818TQ100R

更新时间： 2024-11-17 22:14:35

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		存储内存集成电路静态存储器
页数	文件大小	规格书
20页	319K
描述
128K x 36 and 256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM

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MCM63P818TQ100R 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	LQFP,
针数：	100	Reach Compliance Code：	unknown
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
风险等级：	5.66	Is Samacsys：	N
最长访问时间：	5 ns	其他特性：	PIPELINED ARCHITECTURE
JESD-30 代码：	R-PQFP-G100	JESD-609代码：	e0
长度：	20 mm	内存密度：	4718592 bit
内存集成电路类型：	CACHE SRAM	内存宽度：	18
功能数量：	1	端口数量：	1
端子数量：	100	字数：	262144 words
字数代码：	256000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	256KX18	输出特性：	3-STATE
可输出：	YES	封装主体材料：	PLASTIC/EPOXY
封装代码：	LQFP	封装形状：	RECTANGULAR
封装形式：	FLATPACK, LOW PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	NOT SPECIFIED	认证状态：	Not Qualified
座面最大高度：	1.6 mm	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3.135 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	14 mm	Base Number Matches：	1

MCM63P818TQ100R 数据手册

Order this document

by MCM63P736/D

SEMICONDUCTOR TECHNICAL DATA

MCM63P736

MCM63P818

Product Preview

128K x 36 and 256K x 18 Bit

Pipelined BurstRAM

Synchronous Fast Static RAM

The MCM63P736 and MCM63P818 are 4M bit synchronous fast static RAMs

designed to provide a burstable, high performance, secondary cache for the

PowerPC and other high performance microprocessors. The MCM63P736 is

organized as 128K words of 36 bits each and the MCM63P818 is organized as

256K words of 18 bits each. These devices integrate input registers, an output

circuit for reduced parts count in cache data RAM applications. Synchronous de-

sign allows precise cycle control with the use of an external clock (K).

Addresses (SA), data inputs (DQx), and all control signals except output

enable(G), sleepmode(ZZ), andlinearburstorder(LBO)areclock(K)controlled

through positive–edge–triggered noninverting registers.

TQ PACKAGE

TQFP

CASE 983A–01

ZP PACKAGE

PBGA

CASE 999–01

Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst

addresses can be generated internally by the MCM63P736 and MCM63P818

(burstsequenceoperatesinlinearorinterleavedmodedependentuponthestate

of LBO) and controlled by the burst address advance (ADV) input pin.

Write cycles are internally self–timed and are initiated by the rising edge of the

clock (K) input. This feature eliminates complex off–chip write pulse generation

and provides increased timing flexibility for incoming signals.

Synchronous byte write (SBx), synchronous global write (SGW), and synchro-

nous write enable (SW) are provided to allow writes to either individual bytes or

toallbytes. Thebytesaredesignatedas“a”, “b”, etc. SBacontrolsDQa, SBbcon-

trols DQb, etc. Individual bytes are written if the selected byte writes SBx are as-

serted with SW. All bytes are written if either SGW is asserted or if all SBx and

SW are asserted.

For read cycles, pipelined SRAMs output data is temporarily stored by an

edge–triggeredoutput register and then released to the output buffers at the next

rising edge of clock (K).

The MCM63P736 and MCM63P818 operate from a 3.3 V core power supply

and all outputs operate on a 2.5 V or 3.3 V power supply. All inputs and outputs

are JEDEC standard JESD8–5 compatible.

•

MCM63P736/MCM63P818–133 = 4 ns Access/7.5 ns Cycle (133 MHz)

MCM63P736/MCM63P818–100 = 5 ns Access/10 ns Cycle (100 MHz)

MCM63P736/MCM63P818–66 = 7 ns Access/15 ns Cycle (66 MHz)

3.3 V + 10%, – 5% Core Power Supply, 2.5 V or 3.3 V I/O Supply

ADSP, ADSC, and ADV Burst Control Pins

Selectable Burst Sequencing Order (Linear/Interleaved)

Two–Cycle Deselect Timing

Internally Self–Timed Write Cycle

Byte Write and Global Write Control

Sleep Mode (ZZ)

PB1 Version 2.0 Compatible

JEDEC Standard 119–Pin PBGA and 100–Pin TQFP Packages

•

The PowerPC name is a trademark of IBM Corp., used under license therefrom.

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

10/8/97

Motorola, Inc. 1997

MOTOROLA FAST SRAM

MCM63P736•MCM63P818

12 3 4 5 6 7...20

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与MCM63P818TQ100R相关器件

型号	品牌	获取价格	描述	数据表
MCM63P818TQ133	MOTOROLA	获取价格	128K x 36 and 256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM
MCM63P818TQ133R	MOTOROLA	获取价格	128K x 36 and 256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM
MCM63P818TQ66	MOTOROLA	获取价格	128K x 36 and 256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM
MCM63P818TQ66R	MOTOROLA	获取价格	128K x 36 and 256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM
MCM63P818ZP100	MOTOROLA	获取价格	128K x 36 and 256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM
MCM63P818ZP100R	MOTOROLA	获取价格	128K x 36 and 256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM
MCM63P818ZP133	MOTOROLA	获取价格	128K x 36 and 256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM
MCM63P818ZP133R	MOTOROLA	获取价格	128K x 36 and 256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM
MCM63P818ZP66	MOTOROLA	获取价格	128K x 36 and 256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM
MCM63P818ZP66R	MOTOROLA	获取价格	128K x 36 and 256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM

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