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by MCM63P736/D
SEMICONDUCTOR TECHNICAL DATA
MCM63P736
MCM63P818
Product Preview
128K x 36 and 256K x 18 Bit
Pipelined BurstRAM
Synchronous Fast Static RAM
The MCM63P736 and MCM63P818 are 4M bit synchronous fast static RAMs
designed to provide a burstable, high performance, secondary cache for the
PowerPC and other high performance microprocessors. The MCM63P736 is
organized as 128K words of 36 bits each and the MCM63P818 is organized as
256K words of 18 bits each. These devices integrate input registers, an output
register, a 2–bit address counter, and high speed SRAM onto a single monolithic
circuit for reduced parts count in cache data RAM applications. Synchronous de-
sign allows precise cycle control with the use of an external clock (K).
Addresses (SA), data inputs (DQx), and all control signals except output
enable(G), sleepmode(ZZ), andlinearburstorder(LBO)areclock(K)controlled
through positive–edge–triggered noninverting registers.
TQ PACKAGE
TQFP
CASE 983A–01
ZP PACKAGE
PBGA
CASE 999–01
Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst
addresses can be generated internally by the MCM63P736 and MCM63P818
(burstsequenceoperatesinlinearorinterleavedmodedependentuponthestate
of LBO) and controlled by the burst address advance (ADV) input pin.
Write cycles are internally self–timed and are initiated by the rising edge of the
clock (K) input. This feature eliminates complex off–chip write pulse generation
and provides increased timing flexibility for incoming signals.
Synchronous byte write (SBx), synchronous global write (SGW), and synchro-
nous write enable (SW) are provided to allow writes to either individual bytes or
toallbytes. Thebytesaredesignatedas“a”, “b”, etc. SBacontrolsDQa, SBbcon-
trols DQb, etc. Individual bytes are written if the selected byte writes SBx are as-
serted with SW. All bytes are written if either SGW is asserted or if all SBx and
SW are asserted.
For read cycles, pipelined SRAMs output data is temporarily stored by an
edge–triggeredoutput register and then released to the output buffers at the next
rising edge of clock (K).
The MCM63P736 and MCM63P818 operate from a 3.3 V core power supply
and all outputs operate on a 2.5 V or 3.3 V power supply. All inputs and outputs
are JEDEC standard JESD8–5 compatible.
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MCM63P736/MCM63P818–133 = 4 ns Access/7.5 ns Cycle (133 MHz)
MCM63P736/MCM63P818–100 = 5 ns Access/10 ns Cycle (100 MHz)
MCM63P736/MCM63P818–66 = 7 ns Access/15 ns Cycle (66 MHz)
3.3 V + 10%, – 5% Core Power Supply, 2.5 V or 3.3 V I/O Supply
ADSP, ADSC, and ADV Burst Control Pins
Selectable Burst Sequencing Order (Linear/Interleaved)
Two–Cycle Deselect Timing
Internally Self–Timed Write Cycle
Byte Write and Global Write Control
Sleep Mode (ZZ)
PB1 Version 2.0 Compatible
JEDEC Standard 119–Pin PBGA and 100–Pin TQFP Packages
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The PowerPC name is a trademark of IBM Corp., used under license therefrom.
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
10/8/97
Motorola, Inc. 1997
MOTOROLA FAST SRAM
MCM63P736•MCM63P818
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