Datasheet > MCM63P819KZP166

MCM63P819KZP166

更新时间： 2024-11-19 00:46:35

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		/
页数	文件大小	规格书
20页	395K
描述
128K x 36 and 256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM

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MCM63P819KZP166 数据手册

Freescale Semiconductor, Inc.

SEMICONDUCTOR TECHNICAL DATA

MOTOROLA

Order this document

by MCM63P737K/D

MCM63P737K

MCM63P819K

Advance Information

128K x 36 and 256K x 18 Bit

Pipelined BurstRAM

Synchronous Fast Static RAM

The MCM63P737K and MCM63P819K are 4M–bit synchronous fast static

RAMs designedtoprovideaburstable, highperformance, secondarycache. The

MCM63P737K (organized as 128K words by 36 bits) and the MCM63P819K

(organized as 256K words by 18 bits) integrate input registers, an output register,

a 2–bit address counter, and high speed SRAM onto a single monolithic circuit

for reduced parts count in cache data RAM applications. Synchronous design

allows precise cycle control with the use of an external clock (K).

TQ PACKAGE

TQFP

CASE 983A–01

Addresses (SA), data inputs (DQx), and all control signals except output

enable (G), sleep mode (ZZ), and linear burst order (LBO) are clock (K)

controlled through positive–edge–triggered noninverting registers.

Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst

addresses can be generated internally by the MCM63P737K and MCM63P819K

(burstsequenceoperatesinlinearorinterleavedmodedependentuponthestate

of LBO) and controlled by the burst address advance (ADV) input pin.

Write cycles are internally self–timed and are initiated by the rising edge of the

clock (K) input. This feature eliminates complex off–chip write pulse generation

and provides increased timing flexibility for incoming signals.

ZP PACKAGE

PBGA

CASE 999–02

Synchronous byte write (SBx), synchronous global write (SGW), and synchro-

nous write enable (SW) are provided to allow writes to either individual bytes or

to all bytes. The bytes are designated as “a”, “b”, etc. SBa controls DQa, SBb

controls DQb, etc. Individual bytes are written if the selected byte writes SBx are

asserted with SW. All bytes are written if either SGW is asserted or if all SBx and

SW are asserted.

For read cycles, pipelined SRAMs output data is temporarily stored by an

edge–triggeredoutput register and then released to the output buffers at the next

rising edge of clock (K).

The MCM63P737K and MCM63P819K operate from a 3.3 V core power

supply and all outputs operate on a 2.5 V or 3.3 V power supply. All inputs and

outputs are JEDEC standard JESD8–5 compatible.

•

MCM63P737K/MCM63P819K–166 = 3.5 ns Access/6 ns Cycle (166 MHz)

MCM63P737K/MCM63P819K–150 = 3.8 ns Access/6.7 ns Cycle (150 MHz)

MCM63P737K/MCM63P819K–133 = 4 ns Access/7.5 ns Cycle (133 MHz)

3.3 V +10%, –5% Core Power Supply, 2.5 V or 3.3 V I/O Supply

ADSP, ADSC, and ADV Burst Control Pins

Selectable Burst Sequencing Order (Linear/Interleaved)

Single–Cycle Deselect Timing

Internally Self–Timed Write Cycle

•

Byte Write and Global Write Control

Sleep Mode (ZZ)

JEDEC Standard 100–Pin TQFP and 119–Pin PBGA Packages

This document contains information on a new product. Specifications and information herein are subject to change without notice.

REV 1

1/24/00

Motorola, Inc. 2000

MOTOROLA FAST SRAM

MCM63P737K•MCM63P819K

For More Information On This Product,

Go to: www.freescale.com

12 3 4 5 6 7...20

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与MCM63P819KZP166相关器件

型号	品牌	获取价格	描述	数据表
MCM63P819KZP166R	MOTOROLA	获取价格	128K x 36 and 256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM
MCM63P819TQ133	MOTOROLA	获取价格	256KX18 CACHE SRAM, 4ns, PQFP100, TQFP-100
MCM63P819TQ133R	MOTOROLA	获取价格	256KX18 CACHE SRAM, 4ns, PQFP100, TQFP-100
MCM63P819TQ150	MOTOROLA	获取价格	256KX18 CACHE SRAM, 3.8ns, PQFP100, TQFP-100
MCM63P819TQ150R	MOTOROLA	获取价格	Cache SRAM, 256KX18, 3.8ns, CMOS, PQFP100, TQFP-100
MCM63P819TQ166	MOTOROLA	获取价格	256KX18 CACHE SRAM, 3.5ns, PQFP100, TQFP-100
MCM63P819TQ166R	MOTOROLA	获取价格	256KX18 CACHE SRAM, 3.5ns, PQFP100, TQFP-100
MCM63P819ZP133	MOTOROLA	获取价格	Cache SRAM, 256KX18, 4ns, CMOS, PBGA119, PLASTIC, BGA-119
MCM63P819ZP133R	MOTOROLA	获取价格	Cache SRAM, 256KX18, 4ns, CMOS, PBGA119, PLASTIC, BGA-119
MCM63P819ZP150	MOTOROLA	获取价格	Cache SRAM, 256KX18, 3.8ns, CMOS, PBGA119, PLASTIC, BGA-119

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