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MC74VHC244MR2 PDF预览

MC74VHC244MR2

更新时间: 2024-11-04 14:53:15
品牌 Logo 应用领域
安森美 - ONSEMI 驱动光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
7页 134K
描述
AHC/VHC SERIES, DUAL 4-BIT DRIVER, TRUE OUTPUT, PDSO20, EIAJ, SOIC-20

MC74VHC244MR2 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP,
针数:20Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.21
系列:AHC/VHCJESD-30 代码:R-PDSO-G20
JESD-609代码:e0长度:12.575 mm
逻辑集成电路类型:BUS DRIVER位数:4
功能数量:2端口数量:2
端子数量:20最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):NOT SPECIFIED
传播延迟(tpd):14.5 ns认证状态:Not Qualified
座面最大高度:2.05 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:TIN LEAD
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:5.275 mmBase Number Matches:1

MC74VHC244MR2 数据手册

 浏览型号MC74VHC244MR2的Datasheet PDF文件第2页浏览型号MC74VHC244MR2的Datasheet PDF文件第3页浏览型号MC74VHC244MR2的Datasheet PDF文件第4页浏览型号MC74VHC244MR2的Datasheet PDF文件第5页浏览型号MC74VHC244MR2的Datasheet PDF文件第6页浏览型号MC74VHC244MR2的Datasheet PDF文件第7页 
MC74VHC244  
Octal Bus Buffer  
The MC74VHC244 is an advanced high speed CMOS octal bus  
buffer fabricated with silicon gate CMOS technology.  
The MC74VHC244 is a noninverting 3state buffer, and has two  
activelow output enables. This device is designed to be used with  
3state memory address drivers, etc.  
The internal circuit is composed of three stages, including a buffer  
output which provides high noise immunity and stable output. The  
inputs tolerate voltages up to 7 V, allowing the interface of 5 V systems  
to 3 V systems.  
http://onsemi.com  
MARKING DIAGRAMS  
20  
SOIC20  
DW SUFFIX  
CASE 751D  
High Speed: t = 3.9 ns (Typ) at V = 5 V  
PD  
CC  
VHC244  
AWLYYWWG  
20  
Low Power Dissipation: I = 4 mA (Max) at T = 25°C  
CC  
A
1
High Noise Immunity: V  
= V = 28% V  
NIL CC  
NIH  
1
Power Down Protection Provided on Inputs  
Balanced Propagation Delays  
20  
VHC  
244  
Designed for 2 V to 5.5 V Operating Range  
TSSOP20  
DT SUFFIX  
CASE 948E  
20  
Low Noise: V  
= 0.9 V (Max)  
OLP  
ALYWG  
1
G
Pin and Function Compatible with Other Standard Logic Families  
Latchup Performance Exceeds 300 mA  
ESD Performance: Human Body Model > 2000 V  
Machine Model > 200 V  
1
VHC244 = Specific Device Code  
A
WL, L  
Y
WW, W  
G or G  
= Assembly Location  
= Wafer Lot  
= Year  
= Work Week  
= PbFree Package  
Chip Complexity: 136 FETs  
NLV Prefix for Automotive and Other Applications Requiring  
Unique Site and Control Change Requirements; AECQ100  
Qualified and PPAP Capable  
(Note: Microdot may be in either location)  
These Devices are PbFree and are RoHS Compliant  
PIN ASSIGNMENT  
2
4
6
8
18  
16  
14  
12  
A1  
A2  
A3  
A4  
YA1  
YA2  
YA3  
YA4  
OEA  
A1  
1
2
3
4
5
6
7
8
9
20  
V
CC  
19 OEB  
18 YA1  
17 B4  
16 YA2  
15 B3  
14 YA3  
13 B2  
12 YA4  
11 B1  
YB4  
A2  
YB3  
A3  
DATA  
NONINVERTING  
OUTPUTS  
INPUTS  
YB2  
A4  
11  
13  
15  
17  
9
7
5
3
B1  
B2  
B3  
B4  
YB1  
YB2  
YB3  
YB4  
YB1  
GND 10  
ORDERING INFORMATION  
See detailed ordering and shipping information in the  
Ordering Information Table on page 2 of this data sheet.  
1
OEA  
OEB  
OUTPUT  
19  
ENABLES  
Figure 1. Logic Diagram  
© Semiconductor Components Industries, LLC, 2013  
1
Publication Order Number:  
March, 2013 Rev. 9  
MC74VHC244/D  

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