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MC74VHC257DR2 PDF预览

MC74VHC257DR2

更新时间: 2024-10-31 03:08:39
品牌 Logo 应用领域
安森美 - ONSEMI 复用器
页数 文件大小 规格书
8页 99K
描述
Quad 2-Channel Multiplexer with 3-State Outputs

MC74VHC257DR2 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP16,.25
针数:16Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.39
系列:AHC/VHCJESD-30 代码:R-PDSO-G16
JESD-609代码:e0长度:9.9 mm
负载电容(CL):50 pF逻辑集成电路类型:MULTIPLEXER
最大I(ol):0.008 A湿度敏感等级:1
功能数量:4输入次数:2
输出次数:1端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TAPE AND REEL
峰值回流温度(摄氏度):235电源:2/5.5 V
传播延迟(tpd):14.5 ns认证状态:Not Qualified
座面最大高度:1.75 mm子类别:Multiplexer/Demultiplexers
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3.9 mm
Base Number Matches:1

MC74VHC257DR2 数据手册

 浏览型号MC74VHC257DR2的Datasheet PDF文件第2页浏览型号MC74VHC257DR2的Datasheet PDF文件第3页浏览型号MC74VHC257DR2的Datasheet PDF文件第4页浏览型号MC74VHC257DR2的Datasheet PDF文件第5页浏览型号MC74VHC257DR2的Datasheet PDF文件第6页浏览型号MC74VHC257DR2的Datasheet PDF文件第7页 
MC74VHC257  
Quad 2−Channel Multiplexer  
with 3−State Outputs  
The MC74VHC257 is an advanced high speed CMOS quad  
2−channel multiplexer fabricated with silicon gate CMOS technology.  
It achieves high speed operation similar to equivalent Bipolar  
Schottky TTL while maintaining CMOS low power dissipation.  
It consists of four 2−input digital multiplexers with common select  
(S) and enable (OE) inputs. When (OE) is held High, selection of data  
is inhibited and all the outputs go Low.  
The select decoding determines whether the A or B inputs get routed  
to the corresponding Y outputs.  
The inputs tolerate voltages up to 7 V, allowing the interface of 5 V  
systems to 3 V systems.  
http://onsemi.com  
MARKING DIAGRAMS  
16  
1
9
8
VHC257  
AWLYWW  
SO−16  
D SUFFIX  
CASE 751B  
High Speed: t = 4.1 ns (Typ) at V = 5.0 V  
PD  
CC  
Low Power Dissipation: I = 4.0 mA (Max) at T = 25°C  
CC  
A
16  
9
High Noise Immunity: V  
= V = 28% V  
NIL CC  
NIH  
Power Down Protection Provided on Inputs  
Balanced Propagation Delays  
Designed for 2.0 V to 5.5 V Operating Range  
VHC257  
ALYW  
TSSOP−16  
DT SUFFIX  
CASE 948F  
1
Low Noise: V  
= 0.8 V (Max)  
8
OLP  
Pin and Function Compatible with Other Standard Logic Families  
Latchup Performance Exceeds 300 mA  
ESD Performance: HBM > 2000 V; Machine Model > 200 V  
Chip Complexity: FETs = 100; Equivalent Gates = 25  
9
16  
VHC257  
ALYW  
EIAJ SO−16  
M SUFFIX  
CASE 966  
8
1
V
S
1
2
16  
15  
CC  
A0  
OE  
A3  
B3  
A
L, WL  
Y
= Assembly Location  
= Wafer Lot  
= Year  
B0  
Y0  
3
4
14  
13  
W, WW = Work Week  
ORDERING INFORMATION  
A1  
B1  
Y3  
A2  
5
6
12  
11  
Device  
Package  
Shipping  
MC74VHC257D  
SO−16  
48 Units/Rail  
B2  
Y2  
7
8
10  
9
Y1  
MC74VHC257DR2  
SO−16  
2500 Tape & Reel  
96 Units/Rail  
GND  
MC74VHC257DT  
TSSOP−16  
MC74VHC257DTR2 TSSOP−16 2500 Tape & Reel  
MC74VHC257M EIAJSO−16 50 Units/Rail  
Figure 1. Pin Assignment  
MC74VHC257MEL EIAJSO−16 2000 Tape & Reel  
†For information on tape and reel specifications,  
including part orientation and tape sizes, please  
refer to our Tape and Reel Packaging Specification  
Brochure, BRD8011/D.  
Semiconductor Components Industries, LLC, 2004  
1
Publication Order Number:  
September, 2004 − Rev. 3  
MC74VHC257/D  

MC74VHC257DR2 替代型号

型号 品牌 替代类型 描述 数据表
MC74VHC257DR2G ONSEMI

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