SEMICONDUCTOR TECHNICAL DATA
The MC74VHC245 is an advanced high speed CMOS octal bus
transceiver fabricated with silicon gate CMOS technology. It achieves high
speed operation similar to equivalent Bipolar Schottky TTL while maintaining
CMOS low power dissipation.
It is intended for two–way asynchronous communication between data
buses. The direction of data transmission is determined by the level of the
DIR input. The output enable pin (OE) can be used to disable the device, so
that the buses are effectively isolated.
DW SUFFIX
20–LEAD SOIC PACKAGE
CASE 751D–04
All inputs are equipped with protection circuits against static discharge.
•
•
•
•
•
•
•
•
•
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•
High Speed: t
= 4.0ns (Typ) at V
= 5V
PD
Low Power Dissipation: I
CC
= 4µA (Max) at T = 25°C
CC
A
High Noise Immunity: V
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Designed for 2V to 5.5V Operating Range
= V
= 28% V
NIH
NIL CC
DT SUFFIX
20–LEAD TSSOP PACKAGE
CASE 948E–02
Low Noise: V
= 1.2V (Max)
OLP
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300mA
ESD Performance: HBM > 2000V; Machine Model > 200V
Chip Complexity: 308 FETs or 77 Equivalent Gates
M SUFFIX
20–LEAD SOIC EIAJ PACKAGE
CASE 967–01
APPLICATION NOTES
ORDERING INFORMATION
1. Do not force a signal on an I/O pin when it is an active output, damage may
occur.
2. All floating (high impedence) input or I/O pins must be fixed by means of
pull up or pull down resistors or bus terminator ICs.
MC74VHCXXXDW
MC74VHCXXXDT
MC74VHCXXXM
SOIC
TSSOP
SOIC EIAJ
3. AparasiticdiodeisformedbetweenthebusandV
terminals. Therefore,
CC
the VHC245 cannot be used to interface 5V to 3V systems directly.
PIN ASSIGNMENT
LOGIC DIAGRAM
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
DIR
1
20
V
CC
A1
A2
A3
A4
A5
A6
A7
A8
B1
B2
B3
B4
B5
B6
B7
B8
A1
A2
2
3
19
18
OE
B1
A
DATA
PORT
B
A3
4
17
B2
DATA
PORT
A4
A5
5
16
15
14
13
12
11
B3
B4
B5
B6
B7
B8
6
A6
7
A7
8
1
DIR
OE
A8
9
19
GND
10
FUNCTION TABLE
Control Inputs
Operation
OE
L
DIR
L
Data Transmitted from Bus B to Bus A
Data Transmitted from Bus A to Bus B
Buses Isolated (High–Impedance State)
L
H
H
X
6/97
Motorola, Inc. 1997
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