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MC74LVX574DW PDF预览

MC74LVX574DW

更新时间: 2024-11-14 23:01:35
品牌 Logo 应用领域
安森美 - ONSEMI 触发器逻辑集成电路光电二极管
页数 文件大小 规格书
8页 151K
描述
LOW-VOLTAGE CMOS

MC74LVX574DW 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP20,.4
针数:20Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.13
系列:LV/LV-A/LVX/HJESD-30 代码:R-PDSO-G20
JESD-609代码:e0长度:12.8 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大频率@ Nom-Sup:45000000 Hz最大I(ol):0.004 A
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP20,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3 V传播延迟(tpd):21 ns
认证状态:Not Qualified座面最大高度:2.65 mm
子类别:FF/Latches最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):2.7 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:7.5 mm
Base Number Matches:1

MC74LVX574DW 数据手册

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Order this document  
by MC74LVX574/D  
SEMICONDUCTOR TECHNICAL DATA  
The MC74LVX574 is an advanced high speed CMOS octal flip–flop  
with 3–state outputs. The inputs tolerate voltages up to 7V, allowing the  
interface of 5V systems to 3V systems.  
This 8–bit D–type flip–flop is controlled by a clock pulse input and an  
output enable input. When the output enable input is high, the eight  
outputs are in a high impedance state.  
LOW–VOLTAGE CMOS  
High Speed: t  
= 8.5ns (Typ) at V  
= 3.3V  
PD  
Low Power Dissipation: I  
CC  
= 4µA (Max) at T = 25°C  
CC  
A
Power Down Protection Provided on Inputs  
Balanced Propagation Delays  
DW SUFFIX  
20–LEAD SOIC PACKAGE  
CASE 751D–04  
Low Noise: V  
= 0.8V (Max)  
OLP  
Pin and Function Compatible with Other Standard Logic Families  
Latchup Performance Exceeds 300mA  
ESD Performance: HBM > 2000V; Machine Model > 200V  
DT SUFFIX  
20–LEAD TSSOP PACKAGE  
CASE 948E–02  
PIN NAMES  
Pins  
Function  
OE  
CP  
D0–D7  
O0–O7  
Output Enable Input  
Clock Pulse Input  
Data Inputs  
3–State Latch Outputs  
V
O0  
19  
O1  
18  
O2  
17  
O3  
16  
O4  
15  
O5  
14  
O6  
13  
O7  
12  
CP  
11  
CC  
20  
1
2
3
4
5
6
7
9
8
10  
OE  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
GND  
Figure 1. 20–Lead Pinout (Top View)  
12/98  
Motorola, Inc. 1998  
REV 0  

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LOW-VOLTAGE CMOS