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MC74LVX8051DT PDF预览

MC74LVX8051DT

更新时间: 2024-11-14 22:15:07
品牌 Logo 应用领域
安森美 - ONSEMI 解复用器开关复用器或开关信号电路光电二极管
页数 文件大小 规格书
12页 252K
描述
Analog Multiplexer/Demultiplexer

MC74LVX8051DT 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP, TSSOP16,.25
针数:16Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.52
Is Samacsys:N模拟集成电路 - 其他类型:SINGLE-ENDED MULTIPLEXER
JESD-30 代码:R-PDSO-G16JESD-609代码:e4
长度:5 mm湿度敏感等级:1
信道数量:8功能数量:1
端子数量:16标称断态隔离度:37 dB
通态电阻匹配规范:25 Ω最大通态电阻 (Ron):50 Ω
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:2/6 V认证状态:Not Qualified
座面最大高度:1.2 mm最大信号电流:0.01 A
子类别:Multiplexer or Switches最大供电电流 (Isup):0.16 mA
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2.5 V
标称供电电压 (Vsup):3 V表面贴装:YES
最长断开时间:30 ns最长接通时间:15 ns
技术:CMOS温度等级:MILITARY
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40宽度:4.4 mm
Base Number Matches:1

MC74LVX8051DT 数据手册

 浏览型号MC74LVX8051DT的Datasheet PDF文件第2页浏览型号MC74LVX8051DT的Datasheet PDF文件第3页浏览型号MC74LVX8051DT的Datasheet PDF文件第4页浏览型号MC74LVX8051DT的Datasheet PDF文件第5页浏览型号MC74LVX8051DT的Datasheet PDF文件第6页浏览型号MC74LVX8051DT的Datasheet PDF文件第7页 
High–Performance Silicon–Gate CMOS  
The MC74LVX8051 utilizes silicon–gate CMOS technology to  
achieve fast propagation delays, low ON resistances, and low OFF  
leakage currents. This analog multiplexer/demultiplexer controls  
analog voltages that may vary across the complete power supply range  
http://onsemi.com  
(from V  
to GND).  
CC  
The LVX8051 is similar in pinout to the high–speed HC4051A and  
the metal–gate MC14051B. The Channel–Select inputs determine  
which one of the Analog Inputs/Outputs is to be connected, by means  
of an analog switch, to the Common Output/Input. When the Enable  
pin is HIGH, all analog switches are turned off.  
16–LEAD SOIC  
D SUFFIX  
CASE 751B  
16–LEAD TSSOP  
DT SUFFIX  
CASE 948F  
The Channel–Select and Enable inputs are compatible with standard  
CMOS outputs; with pull–up resistors they are compatible with  
LSTTL outputs.  
PIN CONNECTION AND  
MARKING DIAGRAM (Top View)  
V
X2  
15  
X1  
14  
X0  
13  
X3  
12  
A
B
C
9
CC  
This device has been designed so that the ON resistance (R ) is  
on  
16  
11  
10  
more linear over input voltage than R of metal–gate CMOS analog  
on  
switches.  
Fast Switching and Propagation Speeds  
Low Crosstalk Between Switches  
1
2
3
4
5
6
7
8
Diode Protection on All Inputs/Outputs  
X4  
X6  
X
X7  
X5 Enable NC GND  
Analog Power Supply Range (V  
– GND) = 2.0 to 6.0 V  
CC  
For detailed package marking information, see the Marking  
Diagram section on page 11 of this data sheet.  
Digital (Control) Power Supply Range (V  
CC  
– GND) = 2.0 to 6.0 V  
Improved Linearity and Lower ON Resistance Than Metal–Gate  
Counterparts  
Low Noise  
ORDERING INFORMATION  
In Compliance With the Requirements of JEDEC Standard No. 7A  
Chip Complexity: LVX8051 — 184 FETs or 46 Equivalent Gates  
Device  
Package  
SOIC  
Shipping  
48 Units/Rail  
96 Units/Rail  
MC74LVX8051D  
MC74LVX8051DT  
LOGIC DIAGRAM  
MC74LVX8051  
TSSOP  
Single–Pole, 8–Position Plus Common Off  
13  
X0  
14  
X1  
15  
FUNCTION TABLE – MC74LVX8051  
3
X2  
X3  
X4  
X5  
X6  
X7  
A
COMMON  
OUTPUT/  
INPUT  
X
ANALOG  
INPUTS/  
12  
1
MULTIPLEXER/  
DEMULTIPLEXER  
Control Inputs  
OUTPUTS  
Select  
5
Enable  
C
B
A
ON Channels  
2
L
L
L
L
L
L
L
L
H
L
L
L
L
L
H
H
L
L
H
L
H
L
H
L
H
X
X0  
X1  
X2  
X3  
X4  
X5  
X6  
X7  
NONE  
4
11  
10  
9
CHANNEL  
SELECT  
INPUTS  
L
B
H
H
H
H
X
C
L
6
ENABLE  
H
H
X
PIN 16 = V  
CC  
PIN 8 = GND  
X = Don’t Care  
Semiconductor Components Industries, LLC, 1999  
1
Publication Order Number:  
October, 1999 – Rev. 1.0  
MC74LVX8051/D  

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