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MC74LVX595MEL PDF预览

MC74LVX595MEL

更新时间: 2024-10-03 01:10:47
品牌 Logo 应用领域
安森美 - ONSEMI 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
14页 344K
描述
8−Bit Shift Register

MC74LVX595MEL 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP16,.3
针数:16Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.92
其他特性:SISO OPERATION ALSO AVAILABLE计数方向:RIGHT
系列:LV/LV-A/LVX/HJESD-30 代码:R-PDSO-G16
JESD-609代码:e0长度:10.2 mm
逻辑集成电路类型:SERIAL IN PARALLEL OUT最大频率@ Nom-Sup:90000000 Hz
位数:8功能数量:1
端子数量:16最高工作温度:85 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP16,.3
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3 V
传播延迟(tpd):18.5 ns认证状态:Not Qualified
座面最大高度:2.05 mm子类别:Shift Registers
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):2.7 V表面贴装:YES
技术:CMOS温度等级:OTHER
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:5.275 mm最小 fmax:100 MHz

MC74LVX595MEL 数据手册

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MC74LVX595  
Product Preview  
8−Bit Shift Register with  
Output Storage Register  
(3−State)  
http://onsemi.com  
MARKING DIAGRAMS  
The MC74LVX595 is an advanced high speed 8bit shift register  
with an output storage register fabricated with silicon gate CMOS  
technology.  
The MC74LVX595 contains an 8bit static shift register which  
feeds an 8bit storage register.  
Shift operation is accomplished on the positive going transition of  
the Shift Clock input (SCK). The output register is loaded with the  
contents of the shift register on the positive going transition of the  
Register Clock input (RCK). Since the RCK and SCK signals are  
independent, parallel outputs can be held stable during the shift  
operation. And, since the parallel outputs are 3state, the LVX595 can  
be directly connected to an 8bit bus. This register can be used in  
serialtoparallelconversion, data receivers, etc.  
The internal circuit is composed of three stages, including a buffer  
output which provides high noise immunity and stable output. The  
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V  
systems to 3.0 V systems.  
16  
9
LVX595  
AWLYYWW  
SOIC16  
D SUFFIX  
CASE 751B  
1
8
16  
9
LVX  
595  
TSSOP16  
DT SUFFIX  
CASE 948F  
AWLYWW  
1
8
16  
9
LVX595  
ALYW  
High Speed: f  
Low Power Dissipation: I = 4 mA (Max) at T = 25°C  
High Noise Immunity: V  
= 100 MHz (Typ) at V = 3.3 V  
CC  
max  
SOIC EIAJ16  
M SUFFIX  
CASE 966  
CC  
A
1
8
= V = 28% V  
NIL CC  
NIH  
Power Down Protection Provided on Inputs  
Balanced Propagation Delays  
Designed for 2 V to 3.6 V Operating Range  
A
= Assembly Location  
WL or L = Wafer Lot  
YY or Y = Year  
WW or W = Work Week  
Low Noise: V  
= 1.0 V (Max)  
OLP  
Pin and Function Compatible with Other Standard Logic Families  
Latchup Performance Exceeds 300 mA  
ESD Performance: HBM > 2000 V; Machine Model > 200 V  
ORDERING INFORMATION  
Device  
Package  
Shipping  
MC74LVX595M  
SO EIAJ16 48 Units/Rail  
MC74LVX595MEL  
SO EIAJ16 2000 Units/Reel  
This document contains information on a product under development. ON Semiconductor  
reserves the right to change or discontinue this product without notice.  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
June, 2006 Rev. 2  
MC74LVX595/D  

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