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MC74LVX8051

更新时间: 2024-11-14 22:15:07
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安森美 - ONSEMI 解复用器
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12页 252K
描述
Analog Multiplexer/Demultiplexer

MC74LVX8051 数据手册

 浏览型号MC74LVX8051的Datasheet PDF文件第2页浏览型号MC74LVX8051的Datasheet PDF文件第3页浏览型号MC74LVX8051的Datasheet PDF文件第4页浏览型号MC74LVX8051的Datasheet PDF文件第5页浏览型号MC74LVX8051的Datasheet PDF文件第6页浏览型号MC74LVX8051的Datasheet PDF文件第7页 
High–Performance Silicon–Gate CMOS  
The MC74LVX8051 utilizes silicon–gate CMOS technology to  
achieve fast propagation delays, low ON resistances, and low OFF  
leakage currents. This analog multiplexer/demultiplexer controls  
analog voltages that may vary across the complete power supply range  
http://onsemi.com  
(from V  
to GND).  
CC  
The LVX8051 is similar in pinout to the high–speed HC4051A and  
the metal–gate MC14051B. The Channel–Select inputs determine  
which one of the Analog Inputs/Outputs is to be connected, by means  
of an analog switch, to the Common Output/Input. When the Enable  
pin is HIGH, all analog switches are turned off.  
16–LEAD SOIC  
D SUFFIX  
CASE 751B  
16–LEAD TSSOP  
DT SUFFIX  
CASE 948F  
The Channel–Select and Enable inputs are compatible with standard  
CMOS outputs; with pull–up resistors they are compatible with  
LSTTL outputs.  
PIN CONNECTION AND  
MARKING DIAGRAM (Top View)  
V
X2  
15  
X1  
14  
X0  
13  
X3  
12  
A
B
C
9
CC  
This device has been designed so that the ON resistance (R ) is  
on  
16  
11  
10  
more linear over input voltage than R of metal–gate CMOS analog  
on  
switches.  
Fast Switching and Propagation Speeds  
Low Crosstalk Between Switches  
1
2
3
4
5
6
7
8
Diode Protection on All Inputs/Outputs  
X4  
X6  
X
X7  
X5 Enable NC GND  
Analog Power Supply Range (V  
– GND) = 2.0 to 6.0 V  
CC  
For detailed package marking information, see the Marking  
Diagram section on page 11 of this data sheet.  
Digital (Control) Power Supply Range (V  
CC  
– GND) = 2.0 to 6.0 V  
Improved Linearity and Lower ON Resistance Than Metal–Gate  
Counterparts  
Low Noise  
ORDERING INFORMATION  
In Compliance With the Requirements of JEDEC Standard No. 7A  
Chip Complexity: LVX8051 — 184 FETs or 46 Equivalent Gates  
Device  
Package  
SOIC  
Shipping  
48 Units/Rail  
96 Units/Rail  
MC74LVX8051D  
MC74LVX8051DT  
LOGIC DIAGRAM  
MC74LVX8051  
TSSOP  
Single–Pole, 8–Position Plus Common Off  
13  
X0  
14  
X1  
15  
FUNCTION TABLE – MC74LVX8051  
3
X2  
X3  
X4  
X5  
X6  
X7  
A
COMMON  
OUTPUT/  
INPUT  
X
ANALOG  
INPUTS/  
12  
1
MULTIPLEXER/  
DEMULTIPLEXER  
Control Inputs  
OUTPUTS  
Select  
5
Enable  
C
B
A
ON Channels  
2
L
L
L
L
L
L
L
L
H
L
L
L
L
L
H
H
L
L
H
L
H
L
H
L
H
X
X0  
X1  
X2  
X3  
X4  
X5  
X6  
X7  
NONE  
4
11  
10  
9
CHANNEL  
SELECT  
INPUTS  
L
B
H
H
H
H
X
C
L
6
ENABLE  
H
H
X
PIN 16 = V  
CC  
PIN 8 = GND  
X = Don’t Care  
Semiconductor Components Industries, LLC, 1999  
1
Publication Order Number:  
October, 1999 – Rev. 1.0  
MC74LVX8051/D  

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