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MC74HCT138AD PDF预览

MC74HCT138AD

更新时间: 2024-10-31 22:34:35
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 解码器驱动器解复用器逻辑集成电路光电二极管输入元件
页数 文件大小 规格书
6页 222K
描述
1-of-8 Decoder/Demultiplexer with LSTTL Compatible Inputs

MC74HCT138AD 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:0.150 INCH, PLASTIC, SOIC-16Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.73Is Samacsys:N
其他特性:3 ENABLE INPUTS系列:HCT
JESD-30 代码:R-PDSO-G16JESD-609代码:e0
长度:9.9 mm负载电容(CL):50 pF
逻辑集成电路类型:OTHER DECODER/DRIVER最大I(ol):0.004 A
功能数量:1端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
输出极性:INVERTED封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
电源:5 VProp。Delay @ Nom-Sup:45 ns
传播延迟(tpd):45 ns认证状态:Not Qualified
座面最大高度:1.75 mm子类别:Decoder/Drivers
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
宽度:3.9 mmBase Number Matches:1

MC74HCT138AD 数据手册

 浏览型号MC74HCT138AD的Datasheet PDF文件第2页浏览型号MC74HCT138AD的Datasheet PDF文件第3页浏览型号MC74HCT138AD的Datasheet PDF文件第4页浏览型号MC74HCT138AD的Datasheet PDF文件第5页浏览型号MC74HCT138AD的Datasheet PDF文件第6页 
SEMICONDUCTOR TECHNICAL DATA  
High–Performance Silicon–Gate CMOS  
N SUFFIX  
PLASTIC PACKAGE  
CASE 648–08  
16  
The MC74HCT138A is identical in pinout to the LS138. The HCT138A  
may be used as a level converter for interfacing TTL or NMOS outputs to  
High Speed CMOS inputs.  
The HCT138A decodes a three–bit Address to one–of–eight active–lot  
outputs. This device features three Chip Select inputs, two active–low and  
one active–high to facilitate the demultiplexing, cascading, and chip–select-  
ing functions. The demultiplexing function is accomplished by using the  
Address inputs to select the desired device output; one of the Chip Selects is  
used as a data input while the other Chip Selects are held in their active  
states.  
1
D SUFFIX  
SOIC PACKAGE  
CASE 751B–05  
16  
1
DT SUFFIX  
TSSOP PACKAGE  
CASE 948F–01  
16  
1
Output Drive Capability: 10 LSTTL Loads  
TTL/NMOS Compatible Input Levels  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 4.5 to 5.5 V  
Low Input Current: 1.0 µA  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
Chip Complexity: 122 FETs or 30.5 Equivalent Gates  
ORDERING INFORMATION  
MC74HCTXXXAN  
MC74HCTXXXAD  
Plastic  
SOIC  
MC74HCTXXXADT TSSOP  
PIN ASSIGNMENT  
A0  
A1  
1
2
16  
15  
V
CC  
LOGIC DIAGRAM  
Y0  
3
4
14  
13  
A2  
1
2
3
15  
14  
13  
12  
Y1  
Y2  
A0  
A1  
A2  
Y0  
CS2  
ADDRESS  
INPUTS  
Y1  
Y2  
Y3  
5
6
12  
11  
CS3  
CS1  
Y3  
Y4  
ACTIVE–LOW  
OUTPUTS  
7
8
10  
9
Y7  
Y5  
Y6  
11  
10  
Y4  
Y5  
Y6  
Y7  
GND  
9
7
FUNCTION TABLE  
6
4
Inputs  
Outputs  
CS1  
CS2  
CS3  
CHIP–  
SELECT  
INPUTS  
CS1CS2 CS3 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7  
PIN 16 = V  
PIN 8 = GND  
CC  
X
X
L
X
H
X
H
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
5
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
L
H
H
H
H
L
H
H
H
H
L
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Design Criteria  
Value  
Units  
Internal Gate Count*  
30.5  
1.5  
ea.  
ns  
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
L
L
H
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
L
Internal Gate Propagation Delay  
Internal Gate Power Dissipation  
5.0  
µW  
pJ  
H
H
Speed Power Product  
.0075  
H = high level (steady state)  
L = low level (steady state)  
X = don’t care  
*Equivalent to a two–input NAND gate.  
10/95  
REV 6  
Motorola, Inc. 1995  

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