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MC74HCT138ADTR2G PDF预览

MC74HCT138ADTR2G

更新时间: 2024-11-02 01:18:35
品牌 Logo 应用领域
安森美 - ONSEMI 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
7页 100K
描述
1-of-8 Decoder/ Demultiplexer with LSTTL Compatible Inputs

MC74HCT138ADTR2G 技术参数

是否无铅: 不含铅生命周期:Active
包装说明:TSSOP,针数:16
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:1.46系列:HCT
输入调节:STANDARDJESD-30 代码:R-PDSO-G16
JESD-609代码:e4长度:5 mm
逻辑集成电路类型:OTHER DECODER/DRIVER湿度敏感等级:1
功能数量:1端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
输出极性:INVERTED封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
座面最大高度:1.2 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:4.4 mmBase Number Matches:1

MC74HCT138ADTR2G 数据手册

 浏览型号MC74HCT138ADTR2G的Datasheet PDF文件第2页浏览型号MC74HCT138ADTR2G的Datasheet PDF文件第3页浏览型号MC74HCT138ADTR2G的Datasheet PDF文件第4页浏览型号MC74HCT138ADTR2G的Datasheet PDF文件第5页浏览型号MC74HCT138ADTR2G的Datasheet PDF文件第6页浏览型号MC74HCT138ADTR2G的Datasheet PDF文件第7页 
MC74HCT138A  
1-of-8 Decoder/  
Demultiplexer with LSTTL  
Compatible Inputs  
High−Performance Silicon−Gate CMOS  
www.onsemi.com  
The MC74HCT138A is identical in pinout to the LS138. The  
HCT138A may be used as a level converter for interfacing TTL or  
NMOS outputs to High Speed CMOS inputs.  
The HCT138A decodes a three−bit Address to one−of−eight  
active−lot outputs. This device features three Chip Select inputs, two  
active−low and one active−high to facilitate the demultiplexing,  
cascading, and chip−selecting functions. The demultiplexing function  
is accomplished by using the Address inputs to select the desired  
device output; one of the Chip Selects is used as a data input while the  
other Chip Selects are held in their active states.  
SOIC−16  
D SUFFIX  
CASE 751B  
TSSOP−16  
DT SUFFIX  
CASE 948F  
PIN ASSIGNMENT  
A0  
A1  
1
2
16  
15  
V
CC  
Y0  
Features  
3
4
14  
13  
A2  
Y1  
Y2  
Output Drive Capability: 10 LSTTL Loads  
TTL/NMOS Compatible Input Levels  
CS2  
5
6
7
8
12  
11  
10  
9
CS3  
CS1  
Y3  
Y4  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2 to 6 V  
Y7  
Y5  
Y6  
Low Input Current: 1.0 mA  
GND  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
MARKING DIAGRAMS  
Chip Complexity: 122 FETs or 30.5 Equivalent Gates  
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS  
Compliant  
16  
HCT138AG  
AWLYWW  
LOGIC DIAGRAM  
1
1
2
3
15  
14  
13  
12  
SOIC−16  
A0  
A1  
A2  
Y0  
Y1  
Y2  
Y3  
Y4  
Y5  
Y6  
Y7  
ADDRESS  
INPUTS  
16  
HCT  
138A  
ALYWG  
G
ACTIVE-LOW  
OUTPUTS  
11  
10  
1
TSSOP−16  
9
7
A
WL, L  
YY, Y  
= Assembly Location  
= Wafer Lot  
= Year  
WW, W = Work Week  
6
4
G or G  
= Pb−Free Package  
CS1  
CS2  
CS3  
CHIP-  
SELECT  
INPUTS  
PIN 16 = V  
CC  
PIN 8 = GND  
(Note: Microdot may be in either location)  
5
ORDERING INFORMATION  
See detailed ordering and shipping information on page 5 of  
this data sheet.  
© Semiconductor Components Industries, LLC, 2015  
1
Publication Order Number:  
June, 2015 − Rev. 11  
MC74HCT138A/D  

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