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MC74HCT174A PDF预览

MC74HCT174A

更新时间: 2024-11-04 23:01:35
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 触发器时钟
页数 文件大小 规格书
5页 181K
描述
Hex D Flip-Flop with Common Clock and Reset with LSTTL Compatible Inputs

MC74HCT174A 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
N SUFFIX  
PLASTIC PACKAGE  
CASE 648–08  
16  
High–Performance Silicon–Gate CMOS  
1
The MC74HCT174A is identical in pinout to the LS174. This device may  
be used as a level converter for interfacing TTL or NMOS outputs to High  
Speed CMOS inputs.  
D SUFFIX  
This device consists of six D flip–flops with common Clock and Reset  
inputs. Each flip–flop is loaded with a low–to–high transition of the Clock  
input. Reset is asynchronous and active–low.  
16  
SOIC PACKAGE  
CASE 751B–05  
1
Output Drive Capability: 10 LSTTL Loads  
TTL NMOS Compatible Input Levels  
Outputs Directly Interface to CMOS, NMOS and TTL  
Operating Voltage Range: 4.5 to 5.5 V  
Low Input Current: 1.0 µA  
ORDERING INFORMATION  
MC74HCXXXAN  
MC74HCXXXAD  
Plastic  
SOIC  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
PIN ASSIGNMENT  
Chip Complexity: 178 FETs or 44.5 Equivalent Gates  
RESET  
Q0  
1
2
16  
15  
V
CC  
Q5  
LOGIC DIAGRAM  
D0  
D1  
3
4
5
6
7
8
14  
13  
12  
11  
10  
9
D5  
D4  
3
4
2
5
Q0  
D0  
D1  
D2  
D3  
D4  
D5  
Q1  
Q4  
Q1  
Q2  
Q3  
Q4  
Q5  
D2  
D3  
6
7
DATA  
INPUTS  
NONINVERTING  
OUTPUTS  
Q2  
Q3  
11  
13  
14  
10  
12  
15  
GND  
CLOCK  
FUNCTION TABLE  
9
1
CLOCK  
RESET  
Inputs  
Reset Clock  
Output  
D
Q
PIN 16 = V  
PIN 8 = GND  
CC  
L
X
X
H
L
L
H
L
H
H
H
H
L
X
X
No Change  
No Change  
Design Criteria  
Internal Gate Count*  
Value  
Units  
ea.  
ns  
44.5  
1.5  
Internal Gate Propagation Delay  
Internal Gate Power Dissipation  
Speed Power Product  
0.005  
0.0075  
µW  
pJ  
* Equivalent to a two–input NAND gate.  
10/95  
REV 6  
Motorola, Inc. 1995  

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