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MC74HCT14ADT PDF预览

MC74HCT14ADT

更新时间: 2024-11-18 13:11:19
品牌 Logo 应用领域
安森美 - ONSEMI 触发器
页数 文件大小 规格书
8页 144K
描述
HCT SERIES, HEX 1-INPUT INVERT GATE, PDSO14, TSSOP-14

MC74HCT14ADT 技术参数

是否Rohs认证:符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP, TSSOP14,.25
针数:14Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.18
Is Samacsys:N系列:HCT
JESD-30 代码:R-PDSO-G14JESD-609代码:e4
长度:5 mm负载电容(CL):50 pF
逻辑集成电路类型:INVERTER最大I(ol):0.004 A
湿度敏感等级:1功能数量:6
输入次数:1端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP14,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:RAIL
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
Prop。Delay @ Nom-Sup:48 ns传播延迟(tpd):48 ns
认证状态:Not Qualified施密特触发器:YES
座面最大高度:1.2 mm子类别:Gates
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:4.4 mm
Base Number Matches:1

MC74HCT14ADT 数据手册

 浏览型号MC74HCT14ADT的Datasheet PDF文件第2页浏览型号MC74HCT14ADT的Datasheet PDF文件第3页浏览型号MC74HCT14ADT的Datasheet PDF文件第4页浏览型号MC74HCT14ADT的Datasheet PDF文件第5页浏览型号MC74HCT14ADT的Datasheet PDF文件第6页浏览型号MC74HCT14ADT的Datasheet PDF文件第7页 
High–Performance Silicon–Gate CMOS  
http://onsemi.com  
The MC74HCT14A may be used as a level converter for interfacing  
TTL or NMOS outputs to high–speed CMOS inputs.  
The HCT14A is identical in pinout to the LS14.  
MARKING  
DIAGRAMS  
14  
The HCT14A is useful to “square up” slow input rise and fall times.  
Due to the hysteresis voltage of the Schmitt trigger, the HCT14A finds  
applications in noisy environments.  
PDIP–14  
N SUFFIX  
CASE 646  
MC74HCT14AN  
AWLYYWW  
Output Drive Capability: 10 LSTTL Loads  
TTL/NMOS–Compatible Input Levels  
Outputs Directly Interface to CMOS, NMOS and TTL  
Operating Voltage Range: 4.5 to 5.5 V  
Low Input Current: 1.0 µA  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
Chip Complexity: 72 FETs or 18 Equivalent Gates  
1
14  
SOIC–14  
D SUFFIX  
CASE 751A  
HCT14A  
AWLYWW  
1
A
= Assembly Location  
WL or L = Wafer Lot  
YY or Y = Year  
WW or W = Work Week  
LOGIC DIAGRAM  
1
2
PIN ASSIGNMENT  
A1  
A2  
A3  
A4  
A5  
A6  
Y1  
Y2  
Y3  
Y4  
Y5  
Y6  
A1  
Y1  
1
2
14  
13 A6  
12  
V
CC  
3
4
A2  
Y2  
3
4
Y6  
11 A5  
10 Y5  
5
6
A3  
Y3  
5
6
7
Y = A  
9
8
A4  
Y4  
9
8
GND  
PIN 14 = V  
CC  
PIN 7 = GND  
11  
13  
10  
12  
ORDERING INFORMATION  
Device  
Package  
PDIP–14  
SOIC–14  
SOIC–14  
Shipping  
FUNCTION TABLE  
MC74HCT14AN  
MC74HCT14AD  
MC74HCT14ADR2  
2000 / Box  
55 / Rail  
Input  
A
Output  
Y
2500 / Reel  
L
H
H
L
Semiconductor Components Industries, LLC, 2000  
1
Publication Order Number:  
March, 2000 – Rev. 7  
MC74HCT14A/D  

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