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MC74HCT157AD

更新时间: 2024-11-17 22:34:43
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 解复用器逻辑集成电路光电二极管
页数 文件大小 规格书
5页 131K
描述
Quad 2-Input Data Selector/Multiplexer with LSTTL-Compatible Inputs

MC74HCT157AD 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP,
针数:16Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.29
Is Samacsys:N系列:HCT
JESD-30 代码:R-PDSO-G16JESD-609代码:e0
长度:9.9 mm负载电容(CL):50 pF
逻辑集成电路类型:MULTIPLEXER功能数量:4
输入次数:2输出次数:1
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED传播延迟(tpd):56 ns
认证状态:Not Qualified座面最大高度:1.75 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3.9 mm
Base Number Matches:1

MC74HCT157AD 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
N SUFFIX  
PLASTIC PACKAGE  
CASE 648–08  
16  
High–Performance Silicon–Gate CMOS  
1
The MC74HCT157A is identical in pinout to the LS157. This device may  
be used as a level converter for interfacing TTL or NMOS outputs to High  
Speed CMOS inputs.  
D SUFFIX  
This device routes 2 nibbles (A or B) to a single port (Y) as determined by  
the Select input. The data is presented at the outputs in noninverted form. A  
high level on the Output Enable input sets all four Y outputs to a low level.  
The HCT157A is similar in function to the HC257 which has 3–state  
outputs.  
16  
SOIC PACKAGE  
CASE 751B–05  
1
ORDERING INFORMATION  
MC74HCTXXXAN  
MC74HCTXXXAD  
Plastic  
SOIC  
Output Drive Capability: 10 LSTTL Loads  
TTL NMOS Compatible Input Levels  
Outputs Directly Interface to CMOS, NMOS and TTL  
Operating Voltage Range: 4.5 to 5.5 V  
Low Input Current: 1.0 µA  
PIN ASSIGNMENT  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
SELECT  
A0  
1
2
16  
15  
V
CC  
OUTPUT  
ENABLE  
Chip Complexity: 102 FETs or 25.5 Equivalent Gates  
B0  
Y0  
3
4
14  
13  
A3  
LOGIC DIAGRAM  
B3  
A1  
B1  
5
6
12  
11  
Y3  
A2  
2
A0  
5
A1  
NIBBLE  
A INPUTS  
Y1  
7
8
10  
9
B2  
Y2  
11  
A2  
GND  
14  
A3  
4
Y0  
3
6
7
9
Y1  
Y2  
Y3  
B0  
B1  
B2  
B3  
DATA  
OUTPUTS  
NIBBLE  
B INPUTS  
FUNCTION TABLE  
Inputs  
12  
10  
13  
Output  
Outputs  
Enable Select Y0 – Y3  
PIN 16 = V  
PIN 8 = GND  
CC  
H
L
L
X
L
H
L
A0A3  
B0B3  
1
SELECT  
15  
OUTPUT ENABLE  
X = don’t care  
A0 – A3, B0 – B3 = the levels  
of the respective Data–Word  
Inputs.  
Design Criteria  
Internal Gate Count*  
Value  
25.5  
Unit  
ea  
Internal Gate Propagation Delay  
Internal Gate Power Dissipation  
Speed Power Product  
1.5  
ns  
0.005  
0.0075  
µW  
pJ  
* Equivalent to a two input NAND gate.  
2/97  
REV 7  
Motorola, Inc. 1997  

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