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MC74HCT138A

更新时间： 2024-11-17 23:01:35
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 解码器解复用器
页数 文件大小 规格书
6页 222K
描述
1-of-8 Decoder/Demultiplexer with LSTTL Compatible Inputs

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中文翻译

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MC74HCT138A 数据手册

 浏览型号MC74HCT138A的Datasheet PDF文件第2页浏览型号MC74HCT138A的Datasheet PDF文件第3页浏览型号MC74HCT138A的Datasheet PDF文件第4页浏览型号MC74HCT138A的Datasheet PDF文件第5页浏览型号MC74HCT138A的Datasheet PDF文件第6页 
SEMICONDUCTOR TECHNICAL DATA  
High–Performance Silicon–Gate CMOS  
N SUFFIX  
PLASTIC PACKAGE  
CASE 648–08  
16  
The MC74HCT138A is identical in pinout to the LS138. The HCT138A  
may be used as a level converter for interfacing TTL or NMOS outputs to  
High Speed CMOS inputs.  
The HCT138A decodes a three–bit Address to one–of–eight active–lot  
outputs. This device features three Chip Select inputs, two active–low and  
one active–high to facilitate the demultiplexing, cascading, and chip–select-  
ing functions. The demultiplexing function is accomplished by using the  
Address inputs to select the desired device output; one of the Chip Selects is  
used as a data input while the other Chip Selects are held in their active  
states.  
1
D SUFFIX  
SOIC PACKAGE  
CASE 751B–05  
16  
1
DT SUFFIX  
TSSOP PACKAGE  
CASE 948F–01  
16  
1
•
•
•
•
•
•
Output Drive Capability: 10 LSTTL Loads  
TTL/NMOS Compatible Input Levels  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 4.5 to 5.5 V  
Low Input Current: 1.0 µA  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
Chip Complexity: 122 FETs or 30.5 Equivalent Gates  
ORDERING INFORMATION  
MC74HCTXXXAN  
MC74HCTXXXAD  
Plastic  
SOIC  
MC74HCTXXXADT TSSOP  
PIN ASSIGNMENT  
•
A0  
A1  
1
2
16  
15  
V
CC  
LOGIC DIAGRAM  
Y0  
3
4
14  
13  
A2  
1
2
3
15  
14  
13  
12  
Y1  
Y2  
A0  
A1  
A2  
Y0  
CS2  
ADDRESS  
INPUTS  
Y1  
Y2  
Y3  
5
6
12  
11  
CS3  
CS1  
Y3  
Y4  
ACTIVE–LOW  
OUTPUTS  
7
8
10  
9
Y7  
Y5  
Y6  
11  
10  
Y4  
Y5  
Y6  
Y7  
GND  
9
7
FUNCTION TABLE  
6
4
Inputs  
Outputs  
CS1  
CS2  
CS3  
CHIP–  
SELECT  
INPUTS  
CS1CS2 CS3 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7  
PIN 16 = V  
PIN 8 = GND  
CC  
X
X
L
X
H
X
H
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
5
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
L
H
H
H
H
L
H
H
H
H
L
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Design Criteria  
Value  
Units  
Internal Gate Count*  
30.5  
1.5  
ea.  
ns  
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
L
L
H
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
L
Internal Gate Propagation Delay  
Internal Gate Power Dissipation  
5.0  
µW  
pJ  
H
H
Speed Power Product  
.0075  
H = high level (steady state)  
L = low level (steady state)  
X = don’t care  
*Equivalent to a two–input NAND gate.  
10/95  
REV 6  
Motorola, Inc. 1995  
123456

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