Datasheet > MC74HC533AJ

MC74HC533AJ

更新时间： 2024-10-30 19:07:55

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		逻辑集成电路
页数	文件大小	规格书
7页	212K
描述
D Latch, 1-Func, 8-Bit, CMOS, CDIP20

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技术参数
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MC74HC533AJ 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	DIP, DIP20,.3	Reach Compliance Code：	unknown
风险等级：	5.92	JESD-30 代码：	R-XDIP-T20
JESD-609代码：	e0	逻辑集成电路类型：	D LATCH
位数：	8	功能数量：	1
端子数量：	20	最高工作温度：	85 °C
最低工作温度：	-40 °C	输出特性：	3-STATE
封装主体材料：	CERAMIC	封装代码：	DIP
封装等效代码：	DIP20,.3	封装形状：	RECTANGULAR
封装形式：	IN-LINE	电源：	2/6 V
认证状态：	Not Qualified	子类别：	FF/Latches
表面贴装：	NO	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	Base Number Matches：	1

MC74HC533AJ 数据手册

SEMICONDUCTOR TECHNICAL DATA

High–Performance Silicon–Gate CMOS

J SUFFIX

CERAMIC PACKAGE

CASE 732–03

The MC54/74HC533A is identical in pinout to the LS533. The device

inputs are compatible with standard CMOS outputs; with pullup resistors,

they are compatible with LSTTL outputs.

These latches appear transparent to data (i.e., the outputs change

asynchronously) when Latch Enable is high. The Data appears at the

outputs in inverted form. When Latch Enable goes low, data meeting the

setup and hold time becomes latched.

The Output Enable input does not affect the state of the latches, but when

Output Enable is high, all device outputs are forced to the high-impedance

state. Thus, data may be latched even when the outputs are not enabled.

The HC533A is identical in function to the HC563 but has the data inputs

on the opposite side of the package from the outputs to facilitate PC board

layout.

N SUFFIX

PLASTIC PACKAGE

CASE 738–03

DW SUFFIX

SOIC PACKAGE

CASE 751D–04

ORDERING INFORMATION

This device is similar in function to the HC373A, which has noninverting

outputs.

MC54HCXXXAJ

Ceramic

Plastic

SOIC

MC74HCXXXAN

MC74HCXXXADW

•

Output Drive Capability: 15 LSTTL Loads

Outputs Directly Interface to CMOS, NMOS and TTL

Operating Voltage Range: 2.0 to 6.0 V

Low Input Current: 1.0 µA

High Noise Immunity Characteristic of CMOS Devices

In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

PIN ASSIGNMENT

OUTPUT

ENABLE

•

Chip Complexity: 256 FETs or 64 Equivalent Gates

LOGIC DIAGRAM

LATCH

ENABLE

GND

DATA

INPUTS

INVERTING

OUTPUTS

FUNCTION TABLE

Inputs

Output

Output Latch

Enable Enable

No Change

LATCH ENABLE

PIN 20 = V

PIN 10 = GND

OUTPUT ENABLE

X = Don’t Care

Z = High Impedance

10/95

REV 2

Motorola, Inc. 1995

12 3 4 5 6 7

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与MC74HC533AJ相关器件

型号	品牌	获取价格	描述	数据表
MC74HC533AN	MOTOROLA	获取价格	Octal 3-State Inverting Transparent Latch
MC74HC533DWR2	MOTOROLA	获取价格	HC/UH SERIES, 8-BIT DRIVER, INVERTED OUTPUT, PDSO20, SOIC-20
MC74HC534ADW	MOTOROLA	获取价格	Octal 3-State Inverting D Flip-Flop
MC74HC534ADWR2	MOTOROLA	获取价格	HC/UH SERIES, 8-BIT DRIVER, INVERTED OUTPUT, PDSO20, 0.300 INCH, PLASTIC, SOIC-20
MC74HC534AN	MOTOROLA	获取价格	Octal 3-State Inverting D Flip-Flop
MC74HC534DW	MOTOROLA	获取价格	HC/UH SERIES, 8-BIT DRIVER, INVERTED OUTPUT, PDSO20, SOIC-20
MC74HC534DWD	MOTOROLA	获取价格	IC,FLIP-FLOP,OCTAL,D TYPE,HC-CMOS,SOP,20PIN,PLASTIC
MC74HC534DWDS	MOTOROLA	获取价格	IC,FLIP-FLOP,OCTAL,D TYPE,HC-CMOS,SOP,20PIN,PLASTIC
MC74HC534DWR2	MOTOROLA	获取价格	HC/UH SERIES, 8-BIT DRIVER, INVERTED OUTPUT, PDSO20, SOIC-20
MC74HC534DWS	MOTOROLA	获取价格	D Flip-Flop, 8-Func, Positive Edge Triggered, CMOS, PDSO20

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