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MC74HC540ADWR2 PDF预览

MC74HC540ADWR2

更新时间: 2024-11-17 22:36:35
品牌 Logo 应用领域
安森美 - ONSEMI 总线驱动器总线收发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
8页 149K
描述
Octal 3-State Inverting Buffer/Line Driver/Line Receiver

MC74HC540ADWR2 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOIC-20
针数:20Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:5.11Is Samacsys:N
控制类型:ENABLE LOW系列:HC/UH
JESD-30 代码:R-PDSO-G20JESD-609代码:e0
长度:12.8 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.006 A
湿度敏感等级:1位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:INVERTED封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP20,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):240
电源:2/6 VProp。Delay @ Nom-Sup:28 ns
传播延迟(tpd):120 ns认证状态:Not Qualified
座面最大高度:2.65 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):3 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:7.5 mm
Base Number Matches:1

MC74HC540ADWR2 数据手册

 浏览型号MC74HC540ADWR2的Datasheet PDF文件第2页浏览型号MC74HC540ADWR2的Datasheet PDF文件第3页浏览型号MC74HC540ADWR2的Datasheet PDF文件第4页浏览型号MC74HC540ADWR2的Datasheet PDF文件第5页浏览型号MC74HC540ADWR2的Datasheet PDF文件第6页浏览型号MC74HC540ADWR2的Datasheet PDF文件第7页 
High–Performance Silicon–Gate CMOS  
The MC74HC540A is identical in pinout to the LS540. The device  
inputs are compatible with Standard CMOS outputs. External pullup  
resistors make them compatible with LSTTL outputs.  
The HC540A is an octal inverting buffer/line driver/line receiver  
designed to be used with 3–state memory address drivers, clock  
drivers, and other bus–oriented systems. This device features inputs  
and outputs on opposite sides of the package and two ANDed  
active–low output enables.  
http://onsemi.com  
MARKING  
DIAGRAMS  
20  
PDIP–20  
N SUFFIX  
CASE 738  
MC74HC540AN  
AWLYYWW  
20  
1
1
The HC540A is similar in function to the HC541A, which has  
non–inverting outputs.  
20  
SOIC WIDE–20  
DW SUFFIX  
CASE 751D  
HC540A  
AWLYYWW  
20  
Output Drive Capability: 15 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS and TTL  
Operating Voltage Range: 2 to 6V  
1
1
A
= Assembly Location  
WL = Wafer Lot  
YY = Year  
Low Input Current: 1µA  
High Noise Immunity Characteristic of CMOS Devices  
In Compliance With the JEDEC Standard No. 7A Requirements  
Chip Complexity: 124 FETs or 31 Equivalent Gates  
LOGIC DIAGRAM  
WW = Work Week  
ORDERING INFORMATION  
Device  
Package  
PDIP–20  
Shipping  
2
3
4
5
6
7
8
9
18  
17  
16  
15  
14  
13  
12  
11  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
Y1  
Y2  
Y3  
Y4  
Y5  
Y6  
Y7  
Y8  
MC74HC540AN  
1440 / Box  
38 / Rail  
MC74HC540ADW  
MC74HC540ADWR2  
SOIC–WIDE  
SOIC–WIDE 1000 / Reel  
Data  
Inputs  
Inverting  
Outputs  
1
Output OE1  
OE2  
PIN 20 = V  
CC  
PIN 10 = GND  
Pinout: 20–Lead Packages (Top View)  
Enables  
19  
V
OE2 Y1  
Y2  
17  
Y3  
16  
Y4  
15  
Y5  
14  
Y6  
13  
Y7  
12  
Y8  
11  
CC  
FUNCTION TABLE  
20  
19  
18  
Inputs  
OE1 OE2  
Output Y  
A
L
L
L
L
L
H
X
X
H
L
H
X
X
H
Z
Z
1
2
3
4
5
6
7
9
8
10  
Z = High Impedance  
X = Don’t Care  
OE1 A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8 GND  
Semiconductor Components Industries, LLC, 2000  
1
Publication Order Number:  
March, 2000 – Rev. 7  
MC74HC540A/D  

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