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MC74HC540ADTEL PDF预览

MC74HC540ADTEL

更新时间： 2024-11-18 21:08:19
品牌 Logo 应用领域
安森美 - ONSEMI 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
8页 145K
描述
IC,BUFFER/DRIVER,SINGLE,8-BIT,HC-CMOS,TSSOP,20PIN,PLASTIC

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中文翻译

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MC74HC540ADTEL 技术参数

是否Rohs认证： 符合生命周期：Obsolete
包装说明：TSSOP, TSSOP20,.25Reach Compliance Code：unknown
风险等级：5.84控制类型：ENABLE LOW
JESD-30 代码：R-PDSO-G20JESD-609代码：e4
负载电容（CL）：50 pF逻辑集成电路类型：BUS DRIVER
最大I（ol）：0.006 A位数：8
功能数量：1端子数量：20
最高工作温度：125 °C最低工作温度：-55 °C
输出特性：3-STATE输出极性：INVERTED
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP20,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法：TAPE AND REEL
电源：2/6 VProp。Delay @ Nom-Sup：28 ns
认证状态：Not Qualified子类别：Bus Driver/Transceivers
表面贴装：YES技术：CMOS
温度等级：MILITARY端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.635 mm
端子位置：DUALBase Number Matches：1

MC74HC540ADTEL 数据手册

 浏览型号MC74HC540ADTEL的Datasheet PDF文件第2页浏览型号MC74HC540ADTEL的Datasheet PDF文件第3页浏览型号MC74HC540ADTEL的Datasheet PDF文件第4页浏览型号MC74HC540ADTEL的Datasheet PDF文件第5页浏览型号MC74HC540ADTEL的Datasheet PDF文件第6页浏览型号MC74HC540ADTEL的Datasheet PDF文件第7页 
High–Performance Silicon–Gate CMOS  
The MC74HC540A is identical in pinout to the LS540. The device  
inputs are compatible with Standard CMOS outputs. External pullup  
resistors make them compatible with LSTTL outputs.  
The HC540A is an octal inverting buffer/line driver/line receiver  
designed to be used with 3–state memory address drivers, clock  
drivers, and other bus–oriented systems. This device features inputs  
and outputs on opposite sides of the package and two ANDed  
active–low output enables.  
http://onsemi.com  
MARKING  
DIAGRAMS  
20  
PDIP–20  
N SUFFIX  
CASE 738  
MC74HC540AN  
AWLYYWW  
20  
1
1
The HC540A is similar in function to the HC541A, which has  
non–inverting outputs.  
20  
SOIC WIDE–20  
DW SUFFIX  
CASE 751D  
HC540A  
AWLYYWW  
20  
• Output Drive Capability: 15 LSTTL Loads  
• Outputs Directly Interface to CMOS, NMOS and TTL  
• Operating Voltage Range: 2 to 6V  
1
1
A
= Assembly Location  
WL = Wafer Lot  
YY = Year  
• Low Input Current: 1µA  
• High Noise Immunity Characteristic of CMOS Devices  
• In Compliance With the JEDEC Standard No. 7A Requirements  
• Chip Complexity: 124 FETs or 31 Equivalent Gates  
LOGIC DIAGRAM  
WW = Work Week  
ORDERING INFORMATION  
Device  
Package  
PDIP–20  
Shipping  
2
3
4
5
6
7
8
9
18  
17  
16  
15  
14  
13  
12  
11  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
Y1  
Y2  
Y3  
Y4  
Y5  
Y6  
Y7  
Y8  
MC74HC540AN  
1440 / Box  
38 / Rail  
MC74HC540ADW  
MC74HC540ADWR2  
SOIC–WIDE  
SOIC–WIDE 1000 / Reel  
Data  
Inputs  
Inverting  
Outputs  
1
Output OE1  
OE2  
PIN 20 = V  
CC  
PIN 10 = GND  
Pinout: 20–Lead Packages (Top View)  
Enables  
19  
V
OE2 Y1  
Y2  
17  
Y3  
16  
Y4  
15  
Y5  
14  
Y6  
13  
Y7  
12  
Y8  
11  
CC  
FUNCTION TABLE  
20  
19  
18  
Inputs  
OE1 OE2  
Output Y  
A
L
L
L
L
L
H
X
X
H
L
H
X
X
H
Z
Z
1
2
3
4
5
6
7
9
8
10  
Z = High Impedance  
X = Don’t Care  
OE1 A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8 GND  
Semiconductor Components Industries, LLC, 2000  
1
Publication Order Number:  
March, 2000 – Rev. 7  
MC74HC540A/D  
12345678

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