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MC74HC540N PDF预览

MC74HC540N

更新时间: 2024-11-06 13:11:19
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 驱动器
页数 文件大小 规格书
5页 153K
描述
HC/UH SERIES, 8-BIT DRIVER, INVERTED OUTPUT, PDIP20, PLASTIC, DIP-20

MC74HC540N 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:DIP
包装说明:DIP,针数:20
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.19其他特性:WITH DUAL OUTPUT ENABLE
系列:HC/UHJESD-30 代码:R-PDIP-T20
JESD-609代码:e0长度:26.415 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:INVERTED
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED传播延迟(tpd):38 ns
认证状态:Not Qualified座面最大高度:4.57 mm
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.62 mm
Base Number Matches:1

MC74HC540N 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
High–Performance Silicon–Gate CMOS  
The MC74HC540A is identical in pinout to the LS540. The device inputs  
are compatible with Standard CMOS outputs. External pullup resistors make  
them compatible with LSTTL outputs.  
N SUFFIX  
PLASTIC PACKAGE  
CASE 738–03  
20  
1
The HC540A is an octal inverting buffer/line driver/line receiver designed  
to be used with 3–state memory address drivers, clock drivers, and other  
bus–oriented systems. This device features inputs and outputs on opposite  
sides of the package and two ANDed active–low output enables.  
The HC540A is similar in function to the HC541A, which has non–inverting  
outputs.  
DW SUFFIX  
SOIC PACKAGE  
CASE 751D–04  
20  
1
Output Drive Capability: 15 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS and TTL  
Operating Voltage Range: 2 to 6V  
ORDERING INFORMATION  
MC74HCXXXAN  
MC74HCXXXADW  
Plastic  
SOIC  
Low Input Current: 1µA  
High Noise Immunity Characteristic of CMOS Devices  
In Compliance With the JEDEC Standard No. 7A Requirements  
Chip Complexity: 124 FETs or 31 Equivalent Gates  
FUNCTION TABLE  
Inputs  
LOGIC DIAGRAM  
Output Y  
OE1 OE2  
A
2
3
4
5
6
7
8
9
18  
17  
16  
15  
14  
13  
12  
11  
L
L
L
L
L
H
X
X
H
L
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
Y1  
Y2  
Y3  
Y4  
Y5  
Y6  
Y7  
Y8  
H
X
X
H
Z
Z
Z = High Impedance  
X = Don’t Care  
Data  
Inputs  
Inverting  
Outputs  
1
Output  
Enables  
OE1  
OE2  
PIN 20 = V  
CC  
PIN 10 = GND  
19  
Pinout: 20–Lead Packages (Top View)  
V
OE2  
19  
Y1  
18  
Y2  
17  
Y3  
16  
Y4  
15  
Y5  
14  
Y6  
13  
Y7  
12  
Y8  
11  
CC  
20  
1
2
3
4
5
6
7
9
8
10  
OE1  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
GND  
10/95  
REV 6  
Motorola, Inc. 1995  

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