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MC74HC4020ADR2 PDF预览

MC74HC4020ADR2

更新时间: 2024-09-13 23:01:35
品牌 Logo 应用领域
安森美 - ONSEMI 计数器触发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
8页 170K
描述
14-Stage Binary Ripple Counter

MC74HC4020ADR2 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP16,.25
针数:16Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.03
其他特性:OUTPUTS FROM 12 STAGES AVAILABLE计数方向:UP
系列:HC/UHJESD-30 代码:R-PDSO-G16
JESD-609代码:e0长度:9.9 mm
负载电容(CL):50 pF负载/预设输入:NO
逻辑集成电路类型:BINARY COUNTER最大频率@ Nom-Sup:25000000 Hz
最大I(ol):0.004 A工作模式:ASYNCHRONOUS
湿度敏感等级:1位数:14
功能数量:1端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TAPE AND REEL
峰值回流温度(摄氏度):240电源:2/6 V
传播延迟(tpd):115 ns认证状态:Not Qualified
座面最大高度:1.75 mm子类别:Counters
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):3 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30触发器类型:NEGATIVE EDGE
宽度:3.9 mm最小 fmax:40 MHz
Base Number Matches:1

MC74HC4020ADR2 数据手册

 浏览型号MC74HC4020ADR2的Datasheet PDF文件第2页浏览型号MC74HC4020ADR2的Datasheet PDF文件第3页浏览型号MC74HC4020ADR2的Datasheet PDF文件第4页浏览型号MC74HC4020ADR2的Datasheet PDF文件第5页浏览型号MC74HC4020ADR2的Datasheet PDF文件第6页浏览型号MC74HC4020ADR2的Datasheet PDF文件第7页 
High–Performance Silicon–Gate CMOS  
The MC74C4020A is identical in pinout to the standard CMOS  
MC14020B. The device inputs are compatible with standard CMOS  
outputs; with pullup resistors, they are compatible with LSTTL  
outputs.  
This device consists of 14 master–slave flip–flops with 12 stages  
brought out to pins. The output of each flip–flop feeds the next and the  
frequency at each output is half of that of the preceding one. Reset is  
asynchronous and active–high.  
State changes of the Q outputs do not occur simultaneously because  
of internal ripple delays. Therefore, decoded output signals are subject  
to decoding spikes and may have to be gated with the Clock of the  
HC4020A for some designs.  
http://onsemi.com  
MARKING  
DIAGRAMS  
16  
PDIP–16  
N SUFFIX  
CASE 648  
MC74HC4020AN  
AWLYYWW  
16  
16  
1
1
16  
SO–16  
D SUFFIX  
CASE 751B  
HC4020A  
AWLYWW  
Output Drive Capability: 10 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2 to 6 V  
1
1
16  
HC40  
20A  
ALYW  
TSSOP–16  
DT SUFFIX  
CASE 948F  
Low Input Current: 1 µA  
16  
High Noise Immunity Characteristic of CMOS Devices  
In Compliance With JEDEC Standard No. 7A Requirements  
Chip Complexity: 398 FETs or 99.5 Equivalent Gates  
1
1
A
= Assembly Location  
WL = Wafer Lot  
YY = Year  
LOGIC DIAGRAM  
WW = Work Week  
9
Q1  
7
Q4  
5
FUNCTION TABLE  
Q5  
4
Q6  
Clock  
Reset  
Output State  
6
10  
Q7  
Clock  
L
L
No Charge  
13  
12  
14  
15  
1
Q8  
Advance to Next State  
All Outputs Are Low  
Q9  
X
H
Q10  
Q11  
Q12  
Q13  
Q14  
2
3
ORDERING INFORMATION  
11  
Pin 16 = V  
Pin 8 = GND  
CC  
Reset  
Device  
Package  
PDIP–16  
SOIC–16  
SOIC–16  
TSSOP–16  
Shipping  
MC74HC4020AN  
MC74HC4020AD  
MC74HC4020ADR2  
MC74HC4020ADT  
MC74HC4020ADTR2  
2000 / Box  
48 / Rail  
V
Q11 Q10 Q8  
15 14 13  
Q9 Reset Clock Q1  
CC  
16  
12  
11  
10  
9
2500 / Reel  
96 / Rail  
Pinout: 16–Lead Plastic Package  
TSSOP–16 2500 / Reel  
(Top View)  
1
2
3
4
5
6
7
8
GND  
Q12 Q13 Q14 Q6  
Q5  
Q7  
Q4  
Semiconductor Components Industries, LLC, 2000  
1
Publication Order Number:  
March, 2000 – Rev. 2  
MC74HC4020A/D  

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