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MC74HC4020ND PDF预览

MC74HC4020ND

更新时间: 2024-11-30 13:11:19
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 计数器
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8页 197K
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MC74HC4020ND 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
High–Performance Silicon–Gate CMOS  
N SUFFIX  
PLASTIC PACKAGE  
CASE 648–08  
16  
The MC74C4020A is identical in pinout to the standard CMOS  
MC14020B. The device inputs are compatible with standard CMOS outputs;  
with pullup resistors, they are compatible with LSTTL outputs.  
This device consists of 14 master–slave flip–flops with 12 stages brought  
out to pins. The output of each flip–flop feeds the next and the frequency at  
each output is half of that of the preceding one. Reset is asynchronous and  
active–high.  
1
D SUFFIX  
SOIC PACKAGE  
CASE 751B–05  
16  
1
State changes of the Q outputs do not occur simultaneously because of  
internal ripple delays. Therefore, decoded output signals are subject to  
decoding spikes and may have to be gated with the Clock of the HC4020A  
for some designs.  
DT SUFFIX  
TSSOP PACKAGE  
CASE 948F–01  
16  
1
Output Drive Capability: 10 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2 to 6 V  
ORDERING INFORMATION  
MC74HCXXXXAN  
MC74HCXXXXAD  
Plastic  
SOIC  
Low Input Current: 1 µA  
High Noise Immunity Characteristic of CMOS Devices  
In Compliance With JEDEC Standard No. 7A Requirements  
Chip Complexity: 398 FETs or 99.5 Equivalent Gates  
MC74HCXXXXADT TSSOP  
FUNCTION TABLE  
Clock  
Reset  
Output State  
LOGIC DIAGRAM  
L
L
No Charge  
9
Q1  
Advance to Next State  
All Outputs Are Low  
7
Q4  
X
H
5
Q5  
4
Q6  
6
10  
Q7  
Clock  
13  
12  
14  
15  
1
Q8  
Q9  
Q10  
Q11  
Q12  
Q13  
Q14  
2
3
11  
Pin 16 = V  
Pin 8 = GND  
CC  
Reset  
V
Q11  
15  
Q10  
14  
Q8  
13  
Q9 Reset Clock  
Q1  
9
CC  
16  
12  
11  
10  
Pinout: 16–Lead Plastic Package  
(Top View)  
1
2
3
4
5
6
7
8
GND  
Q12  
Q13  
Q14  
Q6  
Q5  
Q7  
Q4  
10/95  
REV 1  
Motorola, Inc. 1995  

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