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MC74HC4040ADT PDF预览

MC74HC4040ADT

更新时间: 2024-10-31 23:01:35
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 计数器触发器逻辑集成电路光电二极管
页数 文件大小 规格书
8页 219K
描述
12-Stage Binary Ripple Counter

MC74HC4040ADT 技术参数

生命周期:Transferred零件包装代码:TSSOP
包装说明:TSSOP, TSSOP16,.25针数:16
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.13Is Samacsys:N
计数方向:UP系列:HC/UH
JESD-30 代码:R-PDSO-G16JESD-609代码:e0
长度:5 mm负载电容(CL):50 pF
负载/预设输入:NO逻辑集成电路类型:BINARY COUNTER
最大频率@ Nom-Sup:12000000 Hz最大I(ol):0.0024 A
工作模式:ASYNCHRONOUS位数:12
功能数量:1端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH电源:2/6 V
传播延迟(tpd):40 ns认证状态:Not Qualified
座面最大高度:1.2 mm子类别:Counters
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
触发器类型:NEGATIVE EDGE宽度:4.4 mm
最小 fmax:25 MHzBase Number Matches:1

MC74HC4040ADT 数据手册

 浏览型号MC74HC4040ADT的Datasheet PDF文件第2页浏览型号MC74HC4040ADT的Datasheet PDF文件第3页浏览型号MC74HC4040ADT的Datasheet PDF文件第4页浏览型号MC74HC4040ADT的Datasheet PDF文件第5页浏览型号MC74HC4040ADT的Datasheet PDF文件第6页浏览型号MC74HC4040ADT的Datasheet PDF文件第7页 
SEMICONDUCTOR TECHNICAL DATA  
High–Performance Silicon–Gate CMOS  
J SUFFIX  
CERAMIC PACKAGE  
CASE 620–10  
16  
The MC54/74C4040A is identical in pinout to the standard CMOS  
MC14040. The device inputs are compatible with standard CMOS out-  
puts; with pullup resistors, they are compatible with LSTTL outputs.  
This device consists of 12 master–slave flip–flops. The output of each  
flip–flop feeds the next and the frequency at each output is half of that of  
the preceding one. The state counter advances on the negative–going  
edge of the Clock input. Reset is asynchronous and active–high.  
State changes of the Q outputs do not occur simultaneously because of  
internal ripple delays. Therefore, decoded output signals are subject to  
decoding spikes and may have to be gated with the Clock of the  
HC4040A for some designs.  
1
N SUFFIX  
PLASTIC PACKAGE  
CASE 648–08  
16  
1
D SUFFIX  
SOIC PACKAGE  
CASE 751B–05  
16  
Output Drive Capability: 10 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2 to 6 V  
1
Low Input Current: 1 µA  
DT SUFFIX  
TSSOP PACKAGE  
CASE 948F–01  
16  
High Noise Immunity Characteristic of CMOS Devices  
In Compliance With JEDEC Standard No. 7A Requirements  
Chip Complexity: 398 FETs or 99.5 Equivalent Gates  
1
ORDERING INFORMATION  
MC54HCXXXXAJ  
MC74HCXXXXAN  
MC74HCXXXXAD  
Ceramic  
Plastic  
SOIC  
LOGIC DIAGRAM  
9
Q1  
MC74HCXXXXADT TSSOP  
7
Q2  
6
Q3  
5
FUNCTION TABLE  
Q4  
3
10  
Q5  
Q6  
Q7  
Q8  
Q9  
Q10  
Clock  
Clock  
Reset  
Output State  
2
4
L
L
No Charge  
13  
12  
14  
Advance to Next State  
All Outputs Are Low  
X
H
15  
1
Q11  
Q12  
11  
Pin 16 = V  
Pin 8 = GND  
CC  
Reset  
V
Q11  
15  
Q10  
14  
Q8  
13  
Q9 Reset Clock  
Q1  
9
CC  
16  
12  
11  
10  
Pinout: 16–Lead Plastic Package  
(Top View)  
1
2
3
4
5
6
7
8
GND  
Q12  
Q6  
Q5  
Q7  
Q4  
Q3  
Q2  
10/95  
REV 1  
Motorola, Inc. 1995  

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