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MC74HC4040AN PDF预览

MC74HC4040AN

更新时间: 2024-11-20 23:01:35
品牌 Logo 应用领域
安森美 - ONSEMI 计数器
页数 文件大小 规格书
8页 174K
描述
12-Stage Binary Ripple Counter

MC74HC4040AN 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP16,.3
针数:16Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.11
计数方向:UP系列:HC/UH
JESD-30 代码:R-PDIP-T16JESD-609代码:e0
长度:19.175 mm负载电容(CL):50 pF
负载/预设输入:NO逻辑集成电路类型:BINARY COUNTER
最大频率@ Nom-Sup:25000000 Hz最大I(ol):0.004 A
工作模式:ASYNCHRONOUS湿度敏感等级:1
位数:12功能数量:1
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP16,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):235电源:2/6 V
传播延迟(tpd):115 ns认证状态:Not Qualified
座面最大高度:4.44 mm子类别:Counters
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):3 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30触发器类型:NEGATIVE EDGE
宽度:7.62 mm最小 fmax:40 MHz
Base Number Matches:1

MC74HC4040AN 数据手册

 浏览型号MC74HC4040AN的Datasheet PDF文件第2页浏览型号MC74HC4040AN的Datasheet PDF文件第3页浏览型号MC74HC4040AN的Datasheet PDF文件第4页浏览型号MC74HC4040AN的Datasheet PDF文件第5页浏览型号MC74HC4040AN的Datasheet PDF文件第6页浏览型号MC74HC4040AN的Datasheet PDF文件第7页 
High–Performance Silicon–Gate CMOS  
The MC74C4040A is identical in pinout to the standard CMOS  
MC14040. The device inputs are compatible with standard CMOS  
outputs; with pullup resistors, they are compatible with LSTTL  
outputs.  
This device consists of 12 master–slave flip–flops. The output of  
each flip–flop feeds the next and the frequency at each output is half of  
that of the preceding one. The state counter advances on the  
negative–going edge of the Clock input. Reset is asynchronous and  
active–high.  
State changes of the Q outputs do not occur simultaneously because  
of internal ripple delays. Therefore, decoded output signals are subject  
to decoding spikes and may have to be gated with the Clock of the  
HC4040A for some designs.  
http://onsemi.com  
MARKING  
DIAGRAMS  
16  
PDIP–16  
N SUFFIX  
CASE 648  
MC74HC4040AN  
AWLYYWW  
16  
16  
1
1
16  
SO–16  
D SUFFIX  
CASE 751B  
HC4040A  
AWLYWW  
1
Output Drive Capability: 10 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2 to 6 V  
1
16  
HC40  
40A  
ALYW  
TSSOP–16  
DT SUFFIX  
CASE 948F  
16  
Low Input Current: 1 µA  
1
High Noise Immunity Characteristic of CMOS Devices  
In Compliance With JEDEC Standard No. 7A Requirements  
Chip Complexity: 398 FETs or 99.5 Equivalent Gates  
1
A
= Assembly Location  
WL = Wafer Lot  
YY = Year  
LOGIC DIAGRAM  
WW = Work Week  
9
Q1  
7
FUNCTION TABLE  
Q2  
6
Q3  
Clock  
Reset  
Output State  
5
Q4  
L
L
No Charge  
3
10  
Q5  
Clock  
Advance to Next State  
All Outputs Are Low  
2
4
Q6  
X
H
Q7  
13  
12  
14  
15  
1
Q8  
Q9  
Q10  
Q11  
Q12  
ORDERING INFORMATION  
Device  
Package  
PDIP–16  
SOIC–16  
SOIC–16  
TSSOP–16  
Shipping  
11  
Pin 16 = V  
Pin 8 = GND  
CC  
Reset  
MC74HC4040AN  
MC74HC4040AD  
MC74HC4040ADR2  
MC74HC4040ADT  
MC74HC4040ADTR2  
2000 / Box  
48 / Rail  
V
CC  
16  
Q11 Q10 Q8  
15 14 13  
Q9 Reset Clock Q1  
2500 / Reel  
96 / Rail  
12  
11  
10  
9
TSSOP–16 2500 / Reel  
Pinout: 16–Lead Plastic Package  
(Top View)  
1
2
3
4
5
6
7
8
GND  
Q12 Q6  
Q5  
Q7  
Q4  
Q3  
Q2  
Semiconductor Components Industries, LLC, 2000  
1
Publication Order Number:  
May, 2000 – Rev. 3  
MC74HC4040A/D  

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