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MC74HC4046AFG

更新时间： 2024-11-02 05:27:15
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
18页 167K
描述
Phase−Locked Loop

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MC74HC4046AFG 数据手册

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MC74HC4046A  
Phase−Locked Loop  
High−Performance Silicon−Gate CMOS  
The MC74HC4046A is similar in function to the MC14046 Metal  
gate CMOS device. The device inputs are compatible with standard  
CMOS outputs; with pullup resistors, they are compatible with  
LSTTL outputs.  
The HC4046A phase−locked loop contains three phase  
comparators, a voltage−controlled oscillator (VCO) and unity gain  
http://onsemi.com  
MARKING  
DIAGRAMS  
op−amp DEM  
. The comparators have two common signal inputs,  
OUT  
16  
COMP , and SIG . Input SIG and COMP can be used directly  
IN  
IN  
IN  
IN  
PDIP−16  
N SUFFIX  
CASE 648  
coupled to large voltage signals, or indirectly coupled (with a series  
capacitor to small voltage signals). The self−bias circuit adjusts small  
voltage signals in the linear region of the amplifier. Phase comparator  
MC74HC4046AN  
AWLYYWWG  
16  
1
1
1 (an exclusive OR gate) provides a digital error signal PC1  
and  
OUT  
maintains 90 degrees phase shift at the center frequency between  
SIG and COMP signals (both at 50% duty cycle). Phase  
16  
IN  
IN  
SOIC−16  
D SUFFIX  
CASE 751B  
comparator 2 (with leading−edge sensing logic) provides digital error  
signals PC2 and PCP and maintains a 0 degree phase shift  
HC4046AG  
AWLYWW  
16  
OUT  
OUT  
between SIG and COMP signals (duty cycle is immaterial). The  
1
IN  
IN  
1
linear VCO produces an output signal VCO  
whose frequency is  
OUT  
determined by the voltage of input VCO signal and the capacitor  
and resistors connected to pins C1A, C1B, R1 and R2. The unity gain  
IN  
16  
op−amp output DEM  
with an external resistor is used where the  
OUT  
TSSOP−16  
DT SUFFIX  
CASE 948F  
HC40  
46A  
16  
VCO signal is needed but no loading can be tolerated. The inhibit  
IN  
ALYWG  
input, when high, disables the VCO and all op−amps to minimize  
standby power consumption.  
Applications include FM and FSK modulation and demodulation,  
frequency synthesis and multiplication, frequency discrimination,  
tone decoding, data synchronization and conditioning,  
voltage−to−frequency conversion and motor speed control.  
1
G
1
16  
1
SOEIAJ−16  
F SUFFIX  
CASE 966  
16  
74HC4046A  
ALYWG  
Features  
1
• Output Drive Capability: 10 LSTTL Loads  
• Low Power Consumption Characteristic of CMOS Devices  
• Operating Speeds Similar to LSTTL  
A
L, WL  
Y, YY  
= Assembly Location  
= Wafer Lot  
= Year  
• Wide Operating Voltage Range: 3.0 to 6.0 V  
• Low Input Current: 1.0 mA Maximum (except SIG and COMP )  
IN  
IN  
W, WW = Work Week  
G
= Pb−Free Package  
= Pb−Free Package  
• In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
G
(Note: Microdot may be in either location)  
• Low Quiescent Current: 80 mA Maximum (VCO disabled)  
• High Noise Immunity Characteristic of CMOS Devices  
• Diode Protection on all Inputs  
• Chip Complexity: 279 FETs or 70 Equivalent Gates  
• Pb−Free Packages are Available*  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 5 of this data sheet.  
*For additional information on our Pb−Free strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
©
Semiconductor Components Industries, LLC, 2005  
1
Publication Order Number:  
June, 2005 − Rev. 8  
MC74HC4046A/D  
1234567...18

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