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MC74HC4046AFR2 PDF预览

MC74HC4046AFR2

更新时间： 2024-11-21 19:10:43
品牌 Logo 应用领域
安森美 - ONSEMI 光电二极管
页数 文件大小 规格书
16页 289K
描述
PHASE LOCKED LOOP, PDSO16, SOEIAJ-16

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中文翻译

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MC74HC4046AFR2 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：SOIC包装说明：SOP, SOP16,.3
针数：16Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.7
其他特性：CONTAINS THREE PHASE COMPARATORS模拟集成电路 - 其他类型：PHASE LOCKED LOOP
JESD-30 代码：R-PDSO-G16JESD-609代码：e4
长度：10.2 mm功能数量：1
端子数量：16最高工作温度：125 °C
最低工作温度：-55 °C封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP16,.3
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：2/6 V
认证状态：Not Qualified座面最大高度：2.05 mm
子类别：PLL or Frequency Synthesis Circuits最大供电电压 (Vsup)：6 V
最小供电电压 (Vsup)：2 V标称供电电压 (Vsup)：4.5 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：5.275 mmBase Number Matches：1

MC74HC4046AFR2 数据手册

 浏览型号MC74HC4046AFR2的Datasheet PDF文件第2页浏览型号MC74HC4046AFR2的Datasheet PDF文件第3页浏览型号MC74HC4046AFR2的Datasheet PDF文件第4页浏览型号MC74HC4046AFR2的Datasheet PDF文件第5页浏览型号MC74HC4046AFR2的Datasheet PDF文件第6页浏览型号MC74HC4046AFR2的Datasheet PDF文件第7页 
High–Performance Silicon–Gate CMOS  
The MC74HC4046A is similar in function to the MC14046 Metal  
gate CMOS device. The device inputs are compatible with standard  
CMOS outputs; with pullup resistors, they are compatible with  
LSTTL outputs.  
http://onsemi.com  
The HC4046A phase–locked loop contains three phase  
comparators, a voltage–controlled oscillator (VCO) and unity gain  
MARKING  
DIAGRAMS  
16  
op–amp DEM  
. The comparators have two common signal inputs,  
OUT  
COMP ,andSIG .InputSIG andCOMP canbeuseddirectly  
IN IN IN IN  
PDIP–16  
N SUFFIX  
CASE 648  
coupled to large voltage signals, or indirectly coupled (with a series  
capacitor to small voltage signals). The self–bias circuit adjusts small  
voltage signals in the linear region of the amplifier. Phase comparator  
MC74HC4046AN  
AWLYYWW  
16  
16  
1
1
1 (an exclusive OR gate) provides a digital error signal PC1  
and  
OUT  
maintains 90 degrees phase shift at the center frequency between  
SIG and COMP signals (both at 50% duty cycle). Phase  
16  
SO–16  
D SUFFIX  
CASE 751B  
HC4046A  
AWLYWW  
IN  
comparator 2 (with leading–edge sensing logic) provides digital error  
signals PC2 and PCP and maintains a 0 degree phase shift  
IN  
1
1
OUT  
OUT  
16  
between SIG and COMP signals (duty cycle is immaterial). The  
IN IN  
linear VCO produces an output signal VCO  
whose frequency is  
OUT  
HC40  
46A  
ALYW  
TSSOP–16  
DT SUFFIX  
CASE 948F  
determined by the voltage of input VCO signal and the capacitor  
and resistors connected to pins C1A, C1B, R1 and R2. The unity gain  
IN  
16  
1
op–amp output DEM  
with an external resistor is used where the  
OUT  
1
VCO signal is needed but no loading can be tolerated. The inhibit  
IN  
16  
input, when high, disables the VCO and all op–amps to minimize  
standby power consumption.  
Applications include FM and FSK modulation and demodulation,  
frequency synthesis and multiplication, frequency discrimination,  
tone decoding, data synchronization and conditioning,  
voltage–to–frequency conversion and motor speed control.  
SOEIAJ–16  
F SUFFIX  
CASE 966  
74HC4046B  
AWLYWW  
16  
1
1
A
= Assembly Location  
WL = Wafer Lot  
YY = Year  
WW = Work Week  
• Output Drive Capability: 10 LSTTL Loads  
• Low Power Consumption Characteristic of CMOS Devices  
• Operating Speeds Similar to LSTTL  
• Wide Operating Voltage Range: 3.0 to 6.0 V  
• Low Input Current: 1.0 µA Maximum (except SIG and COMP  
)
IN  
IN  
ORDERING INFORMATION  
• In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
Device  
Package  
PDIP–16  
Shipping  
MC74HC4046AN  
MC74HC4046AD  
MC74HC4046ADR2  
MC74HC4046AF  
MC74HC4046AFEL  
2000 / Box  
48 / Rail  
• Low Quiescent Current: 80 µA Maximum (VCO disabled)  
• High Noise Immunity Characteristic of CMOS Devices  
• Diode Protection on all Inputs  
SOIC–16  
SOIC–16  
SOIC–EIAJ  
SOIC–EIAJ  
2500 / Reel  
See Note  
• Chip Complexity: 279 FETs or 70 Equivalent Gates  
NO TAG  
See Note  
NO TAG  
1. For ordering information on the EIAJ version of the  
SOIC packages, please contact your local ON  
Semiconductor representative.  
Semiconductor Components Industries, LLC, 2000  
1
Publication Order Number:  
March, 2000 – Rev. 7  
MC74HC4046A/D  
1234567...16

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与MC74HC4046AFR2相关器件

型号 品牌 获取价格 描述 数据表
MC74HC4046AN ONSEMI

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 		Phase-Locked Loop
MC74HC4046AND MOTOROLA

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 		PLL/Frequency Synthesis Circuit, CMOS, PDIP16
MC74HC4046ANG ONSEMI

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 		Phase−Locked Loop
MC74HC4046B ONSEMI

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 		Phase-Locked Loop
MC74HC4046BDG ONSEMI

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 		Phase-Locked Loop
MC74HC4046BDR2G ONSEMI

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 		Phase-Locked Loop
MC74HC4046BDTG ONSEMI

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 		Phase-Locked Loop
MC74HC4046BDTR2G ONSEMI

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 		Phase-Locked Loop
MC74HC4046ND MOTOROLA

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 		PLL/Frequency Synthesis Circuit, CMOS, PDIP16
MC74HC4046NS MOTOROLA

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 		PLL/Frequency Synthesis Circuit, CMOS, PDIP16

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