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MC74HC368ADT PDF预览

MC74HC368ADT

更新时间: 2024-11-27 23:01:35
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摩托罗拉 - MOTOROLA /
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6页 155K
描述
Hex 3-State Inverting Buffer with Separate 2-Bit and 4-Bit Sections

MC74HC368ADT 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
N SUFFIX  
PLASTIC PACKAGE  
16–LEAD  
CASE 648–08  
High–Performance Silicon–Gate CMOS  
D SUFFIX  
SOIC PACKAGE  
16–LEAD  
The MC74HC368A is identical in pinout to the LS368. The device inputs  
are compatible with standard CMOS outputs; with pullup resistors, they are  
compatible with LSTTL outputs.  
CASE 751B–05  
DT SUFFIX  
TSSOP PACKAGE  
16–LEAD  
This device is arranged into 2–bit and 4–bit sections, each having its own  
active–low Output Enable. When either of the enables is high, the affected  
buffer outputs are placed into high–impedance states. The HC368A has  
inverting outputs.  
CASE 948F–01  
Output Drive Capability: 15 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2 to 6 V  
ORDERING INFORMATION  
MC74HCXXXAN  
MC74HCXXXAD  
MC74HCXXXADT  
Plastic  
SOIC  
TSSOP  
Low Input Current: 1 µA  
High Noise Immunity Characteristic of CMOS Devices  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
PIN ASSIGNMENT  
Chip Complexity: 80 FETs or 20 Equivalent Gates  
OUTPUT  
1
2
16  
15  
V
CC  
OUTPUT  
ENABLE 2  
ENABLE 1  
A0  
LOGIC DIAGRAM  
Y0  
A1  
3
4
5
6
7
8
14  
13  
12  
11  
10  
9
A5  
Y5  
A4  
Y4  
A3  
Y3  
2
4
3
5
A0  
A1  
Y0  
Y1  
Y1  
A2  
Y2  
6
7
9
A2  
A3  
Y2  
Y3  
GND  
10  
12  
11  
FUNCTION TABLE  
A4  
A5  
Y4  
Y5  
Inputs  
Enable 1,  
Enable 2  
Output  
14  
13  
A
Y
L
L
H
L
H
X
H
L
Z
1
OUTPUT ENABLE 1  
OUTPUT ENABLE 2  
PIN 16 = V  
CC  
PIN 8 = GND  
15  
X = don’t care  
Z = high–impedance  
This document contains information on a product under development. Motorola reserves the right to change or  
discontinue this product without notice.  
1/97  
REV 0  
Motorola, Inc. 1997  

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