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MC74HC373AF PDF预览

MC74HC373AF

更新时间: 2024-11-28 05:09:55
品牌 Logo 应用领域
安森美 - ONSEMI 锁存器
页数 文件大小 规格书
10页 120K
描述
Octal 3−State Non−Inverting Transparent Latch High−Performance Silicon−Gate CMOS

MC74HC373AF 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP20,.3
针数:20Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.76
系列:HC/UHJESD-30 代码:R-PDSO-G20
JESD-609代码:e4长度:12.575 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.006 A湿度敏感等级:3
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP20,.3封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:RAIL
峰值回流温度(摄氏度):260电源:2/6 V
Prop。Delay @ Nom-Sup:38 ns传播延迟(tpd):210 ns
认证状态:Not Qualified座面最大高度:2.05 mm
子类别:FF/Latches最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):3 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:5.275 mm

MC74HC373AF 数据手册

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MC74HC373A  
Octal 3−State Non−Inverting  
Transparent Latch  
High−Performance Silicon−Gate CMOS  
The MC74HC373A is identical in pinout to the LS373. The device  
inputs are compatible with standard CMOS outputs; with pullup  
resistors, they are compatible with LSTTL outputs.  
http://onsemi.com  
MARKING  
These latches appear transparent to data (i.e., the outputs change  
asynchronously) when Latch Enable is high. When Latch Enable goes  
low, data meeting the setup and hold time becomes latched.  
The Output Enable input does not affect the state of the latches, but  
when Output Enable is high, all device outputs are forced to the  
high−impedance state. Thus, data may be latched even when the  
outputs are not enabled.  
DIAGRAMS  
20  
20  
PDIP−20  
N SUFFIX  
CASE 738  
MC74HC373AN  
AWLYYWWG  
1
1
The HC373A is identical in function to the HC573A which has the  
data inputs on the opposite side of the package from the outputs to  
facilitate PC board layout.  
20  
SOIC−20  
20  
74HC373A  
AWLYYWWG  
DW SUFFIX  
CASE 751D  
The HC373A is the non−inverting version of the HC533A.  
1
Features  
1
Output Drive Capability: 15 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS and TTL  
Operating Voltage Range: 2.0 to 6.0 V  
20  
HC  
373A  
ALYWG  
G
TSSOP−20  
DT SUFFIX  
CASE 948E  
20  
Low Input Current: 1.0 mA  
High Noise Immunity Characteristic of CMOS Devices  
In Compliance with the JEDEC Standard No. 7.0 A Requirements  
Chip Complexity: 186 FETs or 46.5 Equivalent Gates  
Pb−Free Packages are Available*  
1
1
20  
SOEIAJ−20  
F SUFFIX  
CASE 967  
20  
74HC373A  
AWLYWWG  
1
1
A
WL, L  
YY, Y  
= Assembly Location  
= Wafer Lot  
= Year  
WW, W = Work Week  
G
= Pb−Free Package  
= Pb−Free Package  
G
(Note: Microdot may be in either location)  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 3 of this data sheet.  
*For additional information on our Pb−Free strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
©
Semiconductor Components Industries, LLC, 2005  
1
Publication Order Number:  
July, 2005 − Rev. 12  
MC74HC373A/D  

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